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Visitor
Visitor
8,197 Views
Registered: ‎09-26-2014

AXI4-stream to Video out is set master timing mode, why all output is low?

hi,i want to use  VDMA,VTC ,Video out to realize a simple display in vivado 2014.2.

My idea :the image is stored in frame buffer,and VMDA transports the image data,and video out 's job is to display the image. 

The following tcl codes  create the  block design.the attachment pdf gives layout.I wonder if my block design is correct?

startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 processing_system7_0
endgroup
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" }  [get_bd_cells processing_system7_0]
startgroup
set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {100} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_EN_CLK1_PORT {1}] [get_bd_cells processing_system7_0]
endgroup
set_property location {47 344} [get_bd_ports clk]
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0
endgroup
connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
connect_bd_intf_net [get_bd_intf_pins processing_system7_0/M_AXI_GP0] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI]
startgroup
set_property -dict [list CONFIG.NUM_MI {1} CONFIG.ENABLE_ADVANCED_OPTIONS {0}] [get_bd_cells axi_interconnect_0]
0
endgroup
startgroup
connect_bd_net -net [get_bd_nets processing_system7_0_FCLK_CLK0] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net -net [get_bd_nets processing_system7_0_FCLK_CLK0] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net -net [get_bd_nets processing_system7_0_FCLK_CLK0] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
endgroup
connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK]
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:v_axi4s_vid_out:3.0 v_axi4s_vid_out_0
endgroup
set_property location {4.5 1227 121} [get_bd_cells v_axi4s_vid_out_0]
set_property location {4 1107 432} [get_bd_cells v_axi4s_vid_out_0]
set_property location {1 185 401} [get_bd_cells xlconstant_0]
set_property name VCC [get_bd_cells xlconstant_0]
set_property location {2.5 828 516} [get_bd_cells v_tc_0]
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 clk_wiz_0
endgroup
set_property location {1.5 246 399} [get_bd_cells clk_wiz_0]
delete_bd_objs [get_bd_nets processing_system7_0_FCLK_CLK0]
connect_bd_net [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins clk_wiz_0/clk_in1]
connect_bd_net [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins clk_wiz_0/reset]
startgroup
set_property -dict [list CONFIG.CLKOUT2_USED {true} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {75.000} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {150.000} CONFIG.USE_RESET {false}] [get_bd_cells clk_wiz_0]
delete_bd_objs [get_bd_nets processing_system7_0_FCLK_RESET0_N]
endgroup
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0
endgroup
connect_bd_net [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
connect_bd_net [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins proc_sys_reset_0/ext_reset_in]
connect_bd_net [get_bd_pins clk_wiz_0/locked] [get_bd_pins proc_sys_reset_0/dcm_locked]
startgroup
connect_bd_net [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins axi_interconnect_0/ARESETN]
connect_bd_net -net [get_bd_nets proc_sys_reset_0_interconnect_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
connect_bd_net -net [get_bd_nets proc_sys_reset_0_interconnect_aresetn] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
endgroup
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:v_axi4s_vid_out:3.0 v_axi4s_vid_out_1
endgroup
set_property location {6 1723 523} [get_bd_cells v_axi4s_vid_out_1]
delete_bd_objs [get_bd_cells v_axi4s_vid_out_0]
set_property -dict [list CONFIG.VTG_MASTER_SLAVE {1}] [get_bd_cells v_axi4s_vid_out_1]
set_property location {5 1545 424} [get_bd_cells v_axi4s_vid_out_1]
regenerate_bd_layout
connect_bd_intf_net [get_bd_intf_pins v_tc_0/vtiming_out] [get_bd_intf_pins v_axi4s_vid_out_1/vtiming_in]
connect_bd_net [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins v_axi4s_vid_out_1/aclk]
connect_bd_net -net [get_bd_nets clk_1] [get_bd_ports clk] [get_bd_pins v_axi4s_vid_out_1/vid_io_out_clk]
set_property location {0.5 -9 494} [get_bd_cells VCC]
connect_bd_net -net [get_bd_nets xlconstant_0_dout] [get_bd_pins v_axi4s_vid_out_1/vid_io_out_ce] [get_bd_pins VCC/dout]
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0
endgroup
set_property location {1 174 424} [get_bd_cells xlconstant_0]
set_property name GND [get_bd_nets xlconstant_0_dout]
set_property name GND [get_bd_cells xlconstant_0]
connect_bd_net [get_bd_pins GND/dout] [get_bd_pins v_axi4s_vid_out_1/rst]
connect_bd_net -net [get_bd_nets GND_dout] [get_bd_pins v_axi4s_vid_out_1/fid] [get_bd_pins GND/dout]
connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins v_axi4s_vid_out_1/aresetn]
connect_bd_net -net [get_bd_nets GND] [get_bd_pins v_axi4s_vid_out_1/aclken] [get_bd_pins VCC/dout]
save_bd_design
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_vdma_0
endgroup
set_property location {5 1407 52} [get_bd_cells axi_vdma_0]
set_property -dict [list CONFIG.c_include_s2mm {0}] [get_bd_cells axi_vdma_0]
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins axi_vdma_0/S_AXI_LITE]
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out1] [get_bd_pins axi_vdma_0/s_axi_lite_aclk] [get_bd_pins clk_wiz_0/clk_out1]
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out2] [get_bd_pins axi_vdma_0/m_axi_mm2s_aclk] [get_bd_pins clk_wiz_0/clk_out2]
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out2] [get_bd_pins axi_vdma_0/m_axis_mm2s_aclk] [get_bd_pins clk_wiz_0/clk_out2]
startgroup
endgroup
connect_bd_net -net [get_bd_nets proc_sys_reset_0_peripheral_aresetn] [get_bd_pins axi_vdma_0/axi_resetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1
endgroup
set_property location {5 1359 272} [get_bd_cells axi_interconnect_1]
set_property location {5 1465 726} [get_bd_cells axi_interconnect_1]
set_property -dict [list CONFIG.NUM_MI {1}] [get_bd_cells axi_interconnect_1]
0
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out1] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins clk_wiz_0/clk_out1]
delete_bd_objs [get_bd_nets processing_system7_0_FCLK_CLK1]
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out2] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins clk_wiz_0/clk_out2]
connect_bd_intf_net [get_bd_intf_pins processing_system7_0/S_AXI_HP0] -boundary_type upper [get_bd_intf_pins axi_interconnect_1/M00_AXI]
connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins axi_vdma_0/M_AXI_MM2S]
connect_bd_intf_net [get_bd_intf_pins axi_vdma_0/M_AXIS_MM2S] [get_bd_intf_pins v_axi4s_vid_out_1/video_in]
startgroup
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:vid_io_rtl:1.0 vid_io_out
connect_bd_intf_net [get_bd_intf_pins v_axi4s_vid_out_1/vid_io_out] [get_bd_intf_ports vid_io_out]
endgroup
regenerate_bd_layout
startgroup
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out1] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins clk_wiz_0/clk_out1]
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out1] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins clk_wiz_0/clk_out1]
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out1] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins clk_wiz_0/clk_out1]
endgroup
startgroup
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out2] [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins clk_wiz_0/clk_out2]
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out2] [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins clk_wiz_0/clk_out2]
connect_bd_net -net [get_bd_nets clk_wiz_0_clk_out2] [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins clk_wiz_0/clk_out2]
endgroup

 

 

QQ截图20140926200540.png

QQ截图20140926200606.png

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6 Replies
Highlighted
Visitor
Visitor
8,196 Views
Registered: ‎09-26-2014

the pictures show GUI configration with VDMA and Video Out, i'v read PG044 and PG020 several times, i think i set right. But the all out puts are low. does stream not work or something else? could u give me some advice? thank U.

PS: the Genlock is disabled with setting the VDMA's register space. Using XMD ,the register space‘s value are: MM2S_VDMACR = 00010002h ;

MM2S_VDMASR = 00015021h

MM2S_REG_INDEX = 00000000h ;

PARK_PTR_REG = 00020000h

MM2S_VSIZE =00000300h;

MM2S_HSIZE = 00000800h MM2S_FRMDLY_STRIDE = 00000800h

I tried this video out is set slave,and TPG generate Stream, it dose work. look forward to hear you soon

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Xilinx Employee
Xilinx Employee
8,176 Views
Registered: ‎08-02-2011

If you do a search for AXI Stream to Video Out not locking, you will see a lot of discussion on the topic.

How are you connecting the core to the VTC?

Do you see correct timing signals coming out of the VTC? Are they the right resolution? Are you using the right pixel clock for the VTC and vid_io_out_clk? Does streaming data come out of the VDMA?
www.xilinx.com
Highlighted
Visitor
Visitor
8,163 Views
Registered: ‎09-26-2014

thank  u for reply . i'v seen your ID @any times while i search about vid_out  on the forums.  it must be annoying to answer same question so many times. sorry for that.....ok ,i explain my hw design:

1. VTC and vid_out share same video_clk, the video resolution is 1024*768, so i pick 65Mhz for video clk,no interlace.

2. VTC ports: the "clken","genclk_en","aresetn"  tie to 1'b1; "vitiming_out" connect to "vtiming_in" of Vid_out.

3. Vid_Out: the "aclken","vid_io_out_en" tie to 1'b1; "rst","fid" tie to 1'b0; "aresetn" connect to "peripheral_aresetn" of pro_sys_rest.

4. VTC is set 1024*768 resolution.

5, i didnt debug  if the  timing signals coming out of the VTC is correct, it should be corect as it's configed as i said before.

6. maybe no stream data from VDMA.i not sure for that.

 

 

i just get in touch with zynq,in the past i most used altera's tool . i wonder whether my hw design id correct , it would be kind of u to create my block design  according to the tcl codes which i copied from tcl console in vivado.

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Visitor
Visitor
8,115 Views
Registered: ‎09-26-2014

hi,I checked the VDMA output stream signals ,and found that the TLAST has only  8 times pulse after a TUSER pulse. But  VTC is setted 1024*768. the following are information about my block design.

1. VTC and vid_out share same video_clk, the video resolution is 1024*768, so i pick 65Mhz for video clk,no interlace.

2. VTC ports: the "clken","genclk_en","aresetn"  tie to 1'b1; "vitiming_out" connect to "vtiming_in" of Vid_out.

3. Vid_Out: the "aclken","vid_io_out_en" tie to 1'b1; "rst","fid" tie to 1'b0; "aresetn" connect to "peripheral_aresetn" of pro_sys_rest.

4. VTC is set 1024*768 resolution.

5, i the  timing signals coming out of the VTC is correct and stable.

 

 

 

i just get in touch with zynq,in the past i most used altera's tool . i wonder whether my hw design id correct , it would be kind of u to create my block design  according to the tcl codes which i copied from tcl console in vivado.thank U!

looking forward....

 

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Xilinx Employee
Xilinx Employee
8,098 Views
Registered: ‎08-02-2011

I checked the VDMA output stream signals ,and found that the TLAST has only  8 times pulse after a TUSER pulse

Well that seems like the VDMA is only sending out 8 lines per frame, which isn't good :)

www.xilinx.com
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Visitor
Visitor
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Registered: ‎09-26-2014

thanks, the problem has been resolved,and the cause is that the start address of frame buffer didn't been defined. 

I have another question.

my thought is that  using SelectIO IP  to generate video LVDS signals which is connected with my LCD panel directly,is my thought correct?  

"TPG + VTC + VIDOUT(slave mode) + SelectIO( serialization 7:1) + Clock/Reset " is my block design in vivado 2014.2.

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