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Anusua
Observer
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Registered: ‎06-18-2020

AXI4 stream to video Out has no lock and has underflow

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I am trying to achieve a lock at the AXI4-stream to Video out using a VTC without using a TPG.

The design is supposed to be like VTC + AXI4 stream to Video out + SDI Transmitter to get video on Zynq Ultrascale+ FPGA

Currently the vid_io_out_clk (input clock) to the AXI4-Stream to Video out is connected to the rx_clk to get the lock, later this will be connected to the tx_clk (this is just for debugging purpose)

The Clock to the VTC is also the rx_clk nd the IPs are not used for interlacing Purpose. Video Format used is 1920*1080, Video Format for AXI4 stream to Video out: 1 Pixel per clock, FIFO Depth:1024 and is used in slave timing mode. The Input to the AXI4 stream has Video Signals from the SDI Receiver and has enough data as checked from the ILA. 

For debugging purpose, I have connected a FIFO generator(sync_in_fifo in my design) and the input syncs are from the SDI receiver and the clocks used are the rx_clk, the write enable is set to 1, and the read_enable is connected to vtg_ce. Then I get a lock at the AXI4 stream to video out & no underflow.

But with VTC, I dont get a lock, and also has status: c008f and there is underflow.

How to proceed on getting a lock with a VTC?

I tried with the example designs (https://forums.xilinx.com/t5/Video-and-Audio/Video-Beginner-Series-8-Debugging-the-AXI4-Stream-to-Video-Out/m-p/866346#M20504) and this worked fine.

Hence changed the settings likewise, but without TPG ,and still don’t get a lock.

bd_1.PNG
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florentw
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Moderator
641 Views
Registered: ‎11-09-2015

Hi @Anusua 

It looks fine.

Then it might be the video stream that you are receiving that is over 1080p. You might want to check by replacing the input with a TPG and keeping the same setting for the VTC. If this is working with the TPG set as 1920*1080 then this is probably an issue with the size of the incoming video stream


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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ashokkum
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Registered: ‎04-09-2019

Hello @Anusua ,

Did You check the debug steps addressed in Table C-2 of PG044. Also, let me know the timing mode, that you used in this IP. Hope this IP has to configure for slave mode. please check this once at your end.

With Regards,

Ashok.

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Anusua
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Registered: ‎06-18-2020

I checked the debug steps in the documentation. The only thing which I found important:

https://www.xilinx.com/support/answers/61430.html

and I attach a screenshot of the ILA output which I get from my hardware. Not sure, if this is relevant for Logicore IP AXI4 stream to video out 4.0, because I use that. The timing mode used is the slave timing mode.

Rest other debug steps, to my knowledge, are done correct/verified in my design.

Small update: now the whole design is running on the tx_clk and the tx_clk is locked in phase with the rx_clk.

 

slaveTiming.PNG
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florentw
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Registered: ‎11-09-2015

Hi @Anusua 

What configuration for the AXI4-Stream to Video out did you use?

When using the VTC, did you connect the gen_clken to the AXI4-Stream to Video out?

Looking at the status of the AXI4-Stream to Video out, it seems to the EOL of the VTC is leading. So this would mean that the resolution configured for the VTC is smaller (at least the width) than what is sent through the AXI4-Stream. Did you make sure the VTC is configured properly.

As you have the CTRL interface for the VTC, you need to configure the VTC through SW, you cannot just use the GUI settings. refer to 

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Series-22-Supporting-multiple-video-resolutions-on-ZC702/ba-p/929761 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Anusua
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Registered: ‎06-18-2020

@florentw 

Yes, I connected the gen_clken to the vtg_ce (attached the screenshot)

I attach screenshots for the configuration of VTC and AXI4 stream to video out.

What needs to be done to set the resolution of the VTC correct as to the resolution of the AXI4 stream?

Well, I can peekpoke to the VTC register to change the settings for the software, which I do to set the values.

I attach the values I read or write to the registers.

I write to the register: peekpoke 32 0x80106000 0x7F7EF06

and read back

root@zynqmp-as11:~/das# peekpoke 32 0x80106094
0x4380780

root@zynqmp-as11:~/das# peekpoke 32 0x80106070
0x898

Please mention which other registers need to be set or checked for the VTC.

Also, do I need to have a software driver and a device tree setup for the VTC?

 

bd_2.PNG
config_AXI4streamtoVideoOut.PNG
Vtc_1.PNG
vtc_2.PNG
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florentw
Moderator
Moderator
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Registered: ‎11-09-2015

Hi @Anusua 

It looks fine.

Then it might be the video stream that you are receiving that is over 1080p. You might want to check by replacing the input with a TPG and keeping the same setting for the VTC. If this is working with the TPG set as 1920*1080 then this is probably an issue with the size of the incoming video stream


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Anusua
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Registered: ‎06-18-2020

@florentw 

You are correct, the input video standard was set to 1080p/50 and the VTC was set to 1080p/60. After I change the video standard in my input to 1080p/60, I get a lock on the AXI4 stream to video out.