03-30-2020 09:44 AM
03-31-2020 05:59 AM
MIPI D-PHY spec does not mention any restriction on Intra-Lane limitation.
But the spec define the worst-case of EyeDiagram that should be feed into RX receiver.
Please ensure your system can achieve this.
We have received similar question in the past. Xilinx suggest to make less than +/-2ps. See also UG583 Chapter 5.
05-03-2020 09:50 PM