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yamin.jtekt
Visitor
Visitor
6,976 Views
Registered: ‎03-14-2013

Access at address 3 then 4 of the ROM

Hello,

I Have a ROM and I want to access at the adress 3, and one clock cycle later at the adress 4. (not necessarily one cycle, I can wait I can wait longer if necessary)
How can I do this ?
With a delay block ? But the ROM block has only one input.


Thanks

 

yamin

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10 Replies
austin
Scholar
Scholar
6,967 Views
Registered: ‎02-27-2008

y,

 

It is called synchronous logic.  You may need to design a state machine.

 

Do some reading:  state machines, digital synchronous logic.

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
eilert
Teacher
Teacher
6,956 Views
Registered: ‎08-14-2007

Hi,

the input to the ROM probably surely has more than one wire (otherwise ther wouldn't be an address 3).

So you have to change the number (address) that you feed into that input.

 

How do you create the address value in your design (if you have one)?

What tool are you using?

 

Have a nice synthesis

   Eilert

 

 

yamin.jtekt
Visitor
Visitor
6,955 Views
Registered: ‎03-14-2013

Hi,

 

Thanks for answers.


I explain what I want to do :

I stock a table in the rom :

Adresse | Value
.......1...... | -100.0000
.......2 ......|-90.5234
.......3 ......|-81.0430
.......4 ......|-71.5625
.......5 ......|-62.0859

I need to access the value at adress 3 then 4 and calculate an interpolation between them...
To illustrate what i says, look this schema (right click, view in a new tab to enlarge) :

flow-yamin-rom-double-access.PNG

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eilert
Teacher
Teacher
6,949 Views
Registered: ‎08-14-2007

Hi,

so basically you need a 2to1 mux in front of the ROM.

Then you need some circuit that toggles the mux selection input at the right time.

A simple TFF could do this, but you probably need to do the switching between Addr. 3 and Addr. 4 at specific times.

 

What you have created is a datapath.

What you need is some controll module.

That's generally speaking the FSM mentioned by Austin in his former answer.

 

Or you feed the Mux selection input from an IO, then you can controll it from the outside.

Just like your Modulo Value comes from the outside.

If this value is connected to the values that are fed into the multiplieryou also need to take the multipliers latency into account.

 

Have a nice synthesis

  Eilert

yamin.jtekt
Visitor
Visitor
6,946 Views
Registered: ‎03-14-2013

hi,
thanks for the answer


I've also thought of a mux2to1 in front of the ROM and a demux1to2 behind, control by the same signal, but I don't know how to choose (or create) the selection signal ...

 

Actually I'm not constrained in time. For example when the user input is 1.625 I would like to retrieve the value 3 then the value 4. If the user changes the value of the input (e.g. 3.3750), I store again two values at two different addresses (adress 6 and 7).


The only worry is to detect the moment when I recorded one of two values... When I'm sur that is stored, I switch and store the second value ...

 

I don't see how to do that with a state machine because I don't know how to detect the new user value

flow-yamin-rom-double-access-with-mux.PNG

 

Thanks ! 

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yamin.jtekt
Visitor
Visitor
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Registered: ‎03-14-2013

Nobody ? :s

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louisx
Observer
Observer
6,901 Views
Registered: ‎11-21-2012

Is your problem is "when user input is A value, you will send out the addr 3 and 4 value. And if not A value so you will keep on storing data in ROM???"

So to detect the user input is A or not A you can use the relational block to compare.

sorry if i misunderstand your question.

 

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eilert
Teacher
Teacher
6,887 Views
Registered: ‎08-14-2007

Hi,

so you have discovered the difference between algorhythm design and system design now.

 

Your data input surely has some kind of interface specification.

This might be something simple as "Data changes at a constant rate (sampling frequency)" so there must be some sampling clock you could use for that purpose. In the best case that sampling clock would be your system clock.

There could be some data valid signal, indicating new data words for a single clock cycle, or even a handshake that ensures your module has taken the data from the input, so new data can be sent.

 

This can grow as complex as LAN interfaces, processor bus interfaces (AXI, PLB ...) etc..

 

Interfaces may impact the communication performance of the system.

If you are not sure about the kind of interface you might encounter later, you may implement a simple FIFO interface.

FIFOs are available in the Xilinx Block set.

A simple "WriteEnable, FullFlag - ReadEnable, EmptyFlag" set of controll signals is sufficient.

Your FSM can check the EmptyFlag for available data and then force a read of the FIFO content.After processing the data it may write the results to an output FIFO while monitoring the FullFlag to prevent loss of data.

 

If you do something like this, your data source also needs to provide some write signal and care for the input fifos full flag.

 

This proposal is just one option, there are many other solutions, but any solution has to comply with the interface specification.

_______________

Now about your problems with the algorithm and the ROM.

At first glance I did not notice the interpolation thing.

Let me ask a question about it:

If you have an input value of X that triggers ROM address A and A+n (with n being a constant)

wouldn't the interpolation of the resulting ROM values always give the same result?

Therefore, if you know your ROM values and the constant n, wouldn't the whole implementation thing be reducable into that single ROM anyway?

So the input value X would directly cause the ROM to output the desired interpolation value. 

Correct me if I'm wrong, but after determining the ROM address (output of the Convert block)  everything else is calculations that could be done in advance and stored in a single ROM.

 

This would also simplify your interfacing problem, since you have a simple linear dataflow then.

 

Have a nice synthesis

  Eilert

 

 

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yamin.jtekt
Visitor
Visitor
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Registered: ‎03-14-2013

Sorry, I'm going to try to explain my problem differently.


I have a ROM which store this table : [40 50 60 70]. I only want to read data, not write in the ROM.

So,
--> if I put the adress value at 0, the out of the ROM is 40,
--> if I put the adress value at 1, the out of the ROM is 50,
-- >if I put the adress value at 2, the out of the ROM is 60,
-- >if I put the adress value at 3, the out of the ROM is 70.
I hope you understand me

 

Now, what I want to do is :
I need to collect two data of the ROM. For exemple, i want to collect the data 50 and 60.
So, i must set the adress value at 1 (for collect the data "50").
Only when the data is store, i must set the adress value at 2 (for collect the data "60")

After, I can doing an interpolation with the two values (50 and 60).

My question is : how can i do this ? I don't want use a DUAL RAM (because later i need to collect 4 data, so i want to understand how can i do this)

 

Thank you for all.

 

yamin

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eilert
Teacher
Teacher
2,467 Views
Registered: ‎08-14-2007

Hi,

obviously a Read Only Memory cant be written to. :-)

 

My question was about the algorithm.

 

Like in your example:

If you get the adress 1 and it can be foreseen that you are using adress 2 afterwards, therefore the resulting ROM values of 50 and 60 can be also taken for granted.

Instead of doing the two consecutive reads and interpolating the ROM output data,  the (new) ROM  could hold the interpolation value directly.

 

So, if you get address 1 you could directly read the (linear) interpolated value of 55 from the (new) ROM.

 

This way you save all the circuit for reading a second value from a constant address offset and doing the interpolation on these values.

 

This proposal is based on the fact that you always mentioned the consecutive reads to be on adresses with a constant offset (1) .

Of course it would be different if the consecutive read adresses would both be derived from the incoming data so the offset would be variable too. But you never mentioned such a scenario.

 

If you think that you still need some scheme that uses consecutive reads and you still have the problem that you do not know when your data changes you should stat thinking about your data flow controll (and which signals are needed for that purpose). Then you can start thinking about a FSM that actually performs this task.

 

Have a nice synthesis

  Eilert

 

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