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Observer
Observer
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Registered: ‎06-08-2014

Access to the VTC registers when the video clock is not running

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Hi,

I have a design with a camera with parallel bus (clock, hblank, vblank and data). The clock signal is coming from the camera.

I use the Video Timing Controller IP core (2018.3) to detect the video input timings.

The VTC CLK input is connected to the camera clock and RESET_N is permanently high. The AXI clock and reset are connected to the Zynq AXI bus.

If the camera clock is present everything is fine, but if the camera clock is not present (i.e. the camera hasn't been turned on yet), then a bus fault is generated when accessing the VTC registers (the idea is to use the VTC to detect if the camera is on and generating a video stream).

Reading from the documentation (PG016, page 56):

"The core automatically ensures that the AXI4-Lite transactions completes even if the video processing is stalled with RESETn, CLKEN or with the video clock not running."

So it should be possible to access the VTC registers even without video clock running, but this is not the behaviour I see.

 

Thanks and regards,

Matteo

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @mvitstarware 

Having the VTC to complete the transaction does not mean that you will not have an error on the AXI interface. It will just prevent the system to hand.

However, as if you have no clock or the system is in reset, the value you are reading is invalid. The way the VTC signals that is by giving a slave error SLVERR (0x2) on the AXI interface. This matches the AXI4 spec from ARM:

Used when the access has reached the slave successfully, but the slave wishes to return an error condition to the originating master.

This response is clearly documented in the PG016 under the description for clk and ARESETn.

 

VTC.JPG

 

This response will probably cause the processor to go to an error handler.

The recommendation is to fisrt make sure that the clock is running before reading the VTC register. This is what the HDMI IP is doing under the hood

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
502 Views
Registered: ‎11-09-2015

Hi @mvitstarware 

Having the VTC to complete the transaction does not mean that you will not have an error on the AXI interface. It will just prevent the system to hand.

However, as if you have no clock or the system is in reset, the value you are reading is invalid. The way the VTC signals that is by giving a slave error SLVERR (0x2) on the AXI interface. This matches the AXI4 spec from ARM:

Used when the access has reached the slave successfully, but the slave wishes to return an error condition to the originating master.

This response is clearly documented in the PG016 under the description for clk and ARESETn.

 

VTC.JPG

 

This response will probably cause the processor to go to an error handler.

The recommendation is to fisrt make sure that the clock is running before reading the VTC register. This is what the HDMI IP is doing under the hood

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Observer
Observer
497 Views
Registered: ‎06-08-2014

Hi Florent,

thank you for your reply. I didn't see that paragraph!

I will have a look at the HDMI IP.

 

Thanks,

Matteo

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Moderator
Moderator
494 Views
Registered: ‎11-09-2015

Hi @mvitstarware 

I do not think you will see anything in the HDMI IP as the VTC is part of the IP. I was just mentioning how it is done


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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