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Registered: ‎07-25-2018

Adding video upscaler to HDMI subsystem example on ZCU104 board.

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Hello friends,

 

I want to add a upscaler ip core in between HDMI rx and tx blocks so that i can get a 1080p video as an input and give 4k video as an output.

 

I am using ZCU104 board, and HDMI sub-system example code. I successfully added and configured the upscaler(from VPSS) to the example system. If i set the upscaler input and output parameters as 1080p ---1080p system works fine, but when i try to actually upscale the video and set input output parameters like 1080p --- 4k system doesn't work.

 

I believe the reason for this is HDMI tx block expects the same video resolution as HDMI rx block which is 1080p.

 

My question is which parameters/fuctions on the CPU part i should use or change in order to isolate HDMI rx and tx blocks so that i can achieve 1080p video input from rx and 4k video output from tx. 

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1,580 Views
Registered: ‎07-25-2018

Hi @florentw

 

When i change "LOOPBACK_MODE_EN" parameter as Xud recommended it disables the loopback mode and switches to TX only mode. System only works works with Test Pattern Generator after that, not with the HDMI_RX core. I need to replace Test Pattern Generator with VPSS(scaler mode only) without disabling the loopback mode. But the main problem remains, if i do that, i cant configure HDMI_TX core to accept the video output of the VPSS. I need to know which parameters i should modify in order to make HDMI_TX core to accept different video size than HDMI_RX cores input. After that i need to know which parameters i should modify to set the new video size.

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Registered: ‎11-09-2015

Hi @mert.buyukmihci,

 

You might want to look at this topic and the reply from @xud. I think it might help


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

HI @mert.buyukmihci,

 

Do you have any updates on this?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎07-25-2018
Hello,

I wasn't able to investigate the problem further because i am out of town. But the answer at the link you sent didn't solve the problem. I will provide extra information about the problem when i return.
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1,581 Views
Registered: ‎07-25-2018

Hi @florentw

 

When i change "LOOPBACK_MODE_EN" parameter as Xud recommended it disables the loopback mode and switches to TX only mode. System only works works with Test Pattern Generator after that, not with the HDMI_RX core. I need to replace Test Pattern Generator with VPSS(scaler mode only) without disabling the loopback mode. But the main problem remains, if i do that, i cant configure HDMI_TX core to accept the video output of the VPSS. I need to know which parameters i should modify in order to make HDMI_TX core to accept different video size than HDMI_RX cores input. After that i need to know which parameters i should modify to set the new video size.

View solution in original post

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Registered: ‎07-25-2018

I have managed to bypass the TPG and get the video from HDMI_RX core. Now i can see the input video from HDMI_RX on the screen if i set the VPSS scaler option to 1920x1080 to 1920x1080 and HDMI_TX core parameters to XVIDC_VM_1920x1080_50_P.

 

But the video started blinking, it seems there is a problem with the v_synch. And if i upscale the video (1920x1080 to 3840x2160) and also set the HDMI_TX cores parameters to XVIDC_VM_3840x2160_50_P i cant see any video at all, not even blinking.

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Registered: ‎11-09-2015

Hi @mert.buyukmihci,

 

You might have an issue with your clocking. You need to have 2 different clocking for both TX and RX as you are using different resolutions


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

HI @mert.buyukmihci,

 

Do you have any updates on this?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎07-25-2018

Hi @florentw

 

I don't have any updates, system already has 2 different PLLs feeding TX and RX and debug screen shows that both TX and RX has the correct clock frequency.

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Registered: ‎11-09-2015

Hi @mert.buyukmihci,

 

If you can get the TPG to work you should be able to replace it with the VPSS. The application should be similar


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Highlighted
Moderator
Moderator
1,046 Views
Registered: ‎11-09-2015

Hi @mert.buyukmihci,

 

Do you have any updates on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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