07-31-2021 12:23 PM
Hello dear engineers,
I am looking for some example block design that has implemented the multi-VDMA block design. So far, I have used a single VDMA block design with a "Test Pattern Generator" block and have output over an LCD monitor.
I have found some Xilinx documentation on how to make the design with multiple VDMA, but none of them provide an example of block design and Xilinx SDK driver.
Your help is appreciated.
08-01-2021 12:11 AM
08-01-2021 07:02 AM - edited 08-01-2021 07:04 AM
So far I have been able to have the flow of data using a single VDMA with 1080P@60fps. Then I have added the second VDMA. But unbelievably there was lag so that data flow has downgraded to 10fps. Now I am looking for some details that have caused the lag. so I am looking for some new designs based on the Vivado 2018.1 to 2020.2. Of course, those designs don't provide any ready-to-use block design, but some bitstream. What I am looking for is either a "from scratch to goal" or a "ready to use block design". I have read them in advance. Unfortunately, these documents didn't really help.
08-01-2021 09:51 PM
You have to take care of memory bandwidth while working with multiple memory operation designs. The downgrade of FPS is due to insufficient bandwidth availability or improper optimization of the memory data path. Also multiple memory operations occur in one-after-another fashion. Meaning, one operation has to wait until the current memory operation completes.
I think there are no exact "ready to use designs" but xapp741 and xapp792 provide a good starting point for the multi-VDMA design. I would recommend you to check these xapp properly.