cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
2,736 Views
Registered: ‎07-05-2017

Anyone has success in configuring VDMA, Video Timing Conroller and ADV7511 from Petalinux enviorment on Zedboard?

Jump to solution

Has Anyone been able to configure the VDMA, Video Timing Conroller and ADV7511 from Petalinux environment?

 

I tried to take the bare metal code that puts line patterns on HDMI and ported it to Petalinux environment. I think I'm following the register configurations per the spec sheets, but I don't see any patterns come out on the HDMI. Has anyone had success in this area?

 

Thanks!

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
2,176 Views
Registered: ‎11-09-2015

HI @aynilian,

 

Thank you for sharing your findings with the community. I am sure this can be helpful for another member ;)

 

Let me know if you are facing issues in the next steps and please share your final results :)

 

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

18 Replies
Highlighted
Moderator
Moderator
2,685 Views
Registered: ‎11-09-2015

Hi @aynilian,

 

Can you have it working first in bare metal?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Explorer
Explorer
2,668 Views
Registered: ‎07-05-2017

Hi Florentw,

The bare metal works, I ported the bare metal ("ZedBoard HDMI VIPP, Vivado 2014.1") and rewrote the code for the Petalinux platform. The bare metal works most of the time. In bare metal runs, I just have to power cycle the board, program and load the software code to make it work; otherwise I get the underflow flag going up and down and the lock bit is not locked.

 

To port the code, I just had to figure out the bare metal code and see what it was doing to the adv7511 registers using the iic interface, and Axi interface to VDMA Iand VTC IP blocks. The control register I read back from the VDMA block indicates that the VDMA engine is running. the VDMA MM2S_ISR register is 0 means the "Halt" bit is 0.  I will send you a dump of register read back values on VDMA and VTC IP blocks.

 

Thanks,

Aynilian

0 Kudos
Highlighted
Moderator
Moderator
2,648 Views
Registered: ‎11-09-2015

HI @aynilian,

 

Do you have any updates on this? Do you have the log for the VDMA?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Explorer
Explorer
2,640 Views
Registered: ‎07-05-2017

Hi florentw,

 

Here are the dumps of the registers:

 

VTC REGISTER after initialization:

 

VTC Registers after initilization

 

and the VDMA Registers are in:

Screenshot from_vdma_dump.png

 

According to MM2S_DMACR = 0x00010003, this register indicates the bit-0 R/S is Set.

 

 

 

 

This is a snippet of the code where the ADV7511 chip gets initialized through the IIC controller with the values in this array: I included it here since the IIC bus was verified with a logic analyzer and the data matches the array configuration below in the code.

 

#define ADV7511_ADDR   0x72
#define CARRIER_HDMI_OUT_CONFIG_LEN  (40)
uint8_t carrier_hdmi_out_config[CARRIER_HDMI_OUT_CONFIG_LEN][3] =
{
    {ADV7511_ADDR>>1, 0x15, 0x01}, // Input YCbCr 4:2:2 with seperate syncs
    {ADV7511_ADDR>>1, 0x16, 0x38}, // Output format 444, Input Color Depth = 8
                                   //    R0x16[  7] = Output Video Format = 0 (444)
                                   //    R0x16[5:4] = Input Video Color Depth = 11 (8 bits/color)
                                   //    R0x16[3:2] = Input Video Style = 10 (style 1)
                                   //    R0x16[  1] = DDR Input Edge = 0 (falling edge)
                                   //    R0x16[  0] = Output Color Space = 0 (RGB)
#if 0
    // HDTV YCbCr (16to235) to RGB (0to255)
    {ADV7511_ADDR>>1, 0x18, 0xE7}, // Color Space Conversion
                                   //    R0x18[  7] = CSC enable = 1 (CSC enabled)
                                   //    R0x18[6:5] = CSC Scaling Factor = 11 (+/- 4.0, -16384 - 16380)
                                   //    R0x18[4:0] = CSC coefficient A1[12:8] = 00111
    {ADV7511_ADDR>>1, 0x19, 0x34}, //    R0x19[7:0] = CSC coefficient A1[ 7:0] =      00110100
    {ADV7511_ADDR>>1, 0x1A, 0x04}, //    R0x1A[  5] = CSC coefficient update
                                   //    R0x1A[4:0] = CSC coefficient A2[12:8] = 00100
    {ADV7511_ADDR>>1, 0x1B, 0xAD}, //    R0x1B[7:0] = CSC coefficient A2[ 7:0] =      10101101
    {ADV7511_ADDR>>1, 0x1C, 0x00}, //    R0x1C[4:0] = CSC coefficient A3[12:8] = 00000
    {ADV7511_ADDR>>1, 0x1D, 0x00}, //    R0x1D[7:0] = CSC coefficient A3[ 7:0] =      00000000
    {ADV7511_ADDR>>1, 0x1E, 0x1C}, //    R0x1E[4:0] = CSC coefficient A4[12:8] = 11100
    {ADV7511_ADDR>>1, 0x1F, 0x1B}, //    R0x1F[7:0] = CSC coefficient A4[ 7:0] =      00011011
    {ADV7511_ADDR>>1, 0x20, 0x1D}, //    R0x20[4:0] = CSC coefficient B1[12:8] = 11101
    {ADV7511_ADDR>>1, 0x21, 0xDC}, //    R0x21[7:0] = CSC coefficient B1[ 7:0] =      11011100
    {ADV7511_ADDR>>1, 0x22, 0x04}, //    R0x22[4:0] = CSC coefficient B2[12:8] = 00100
    {ADV7511_ADDR>>1, 0x23, 0xAD}, //    R0x23[7:0] = CSC coefficient B2[ 7:0] =      10101101
    {ADV7511_ADDR>>1, 0x24, 0x1F}, //    R0x24[4:0] = CSC coefficient B3[12:8] = 11111
    {ADV7511_ADDR>>1, 0x25, 0x24}, //    R0x25[7:0] = CSC coefficient B3[ 7:0] =      00100100
    {ADV7511_ADDR>>1, 0x26, 0x01}, //    R0x26[4:0] = CSC coefficient B4[12:8] = 00001
    {ADV7511_ADDR>>1, 0x27, 0x35}, //    R0x27[7:0] = CSC coefficient B4[ 7:0] =      00110101
    {ADV7511_ADDR>>1, 0x28, 0x00}, //    R0x28[4:0] = CSC coefficient C1[12:8] = 00000
    {ADV7511_ADDR>>1, 0x29, 0x00}, //    R0x29[7:0] = CSC coefficient C1[ 7:0] =      00000000
    {ADV7511_ADDR>>1, 0x2A, 0x04}, //    R0x2A[4:0] = CSC coefficient C2[12:8] = 00100
    {ADV7511_ADDR>>1, 0x2B, 0xAD}, //    R0x2B[7:0] = CSC coefficient C2[ 7:0] =      10101101
    {ADV7511_ADDR>>1, 0x2C, 0x08}, //    R0x2C[4:0] = CSC coefficient C3[12:8] = 01000
    {ADV7511_ADDR>>1, 0x2D, 0x7C}, //    R0x2D[7:0] = CSC coefficient C3[ 7:0] =      01111100
    {ADV7511_ADDR>>1, 0x2E, 0x1B}, //    R0x2E[4:0] = CSC coefficient C4[12:8] = 11011
    {ADV7511_ADDR>>1, 0x2F, 0x77}, //    R0x2F[7:0] = CSC coefficient C4[ 7:0] =      01110111
#else
    // HDTV YCbCr (16to235) to RGB (16to235)
    {ADV7511_ADDR>>1, 0x18, 0xAC},
    {ADV7511_ADDR>>1, 0x19, 0x53},
    {ADV7511_ADDR>>1, 0x1A, 0x08},
    {ADV7511_ADDR>>1, 0x1B, 0x00},
    {ADV7511_ADDR>>1, 0x1C, 0x00},
    {ADV7511_ADDR>>1, 0x1D, 0x00},
    {ADV7511_ADDR>>1, 0x1E, 0x19},
    {ADV7511_ADDR>>1, 0x1F, 0xD6},
    {ADV7511_ADDR>>1, 0x20, 0x1C},
    {ADV7511_ADDR>>1, 0x21, 0x56},
    {ADV7511_ADDR>>1, 0x22, 0x08},
    {ADV7511_ADDR>>1, 0x23, 0x00},
    {ADV7511_ADDR>>1, 0x24, 0x1E},
    {ADV7511_ADDR>>1, 0x25, 0x88},
    {ADV7511_ADDR>>1, 0x26, 0x02},
    {ADV7511_ADDR>>1, 0x27, 0x91},
    {ADV7511_ADDR>>1, 0x28, 0x1F},
    {ADV7511_ADDR>>1, 0x29, 0xFF},
    {ADV7511_ADDR>>1, 0x2A, 0x08},
    {ADV7511_ADDR>>1, 0x2B, 0x00},
    {ADV7511_ADDR>>1, 0x2C, 0x0E},
    {ADV7511_ADDR>>1, 0x2D, 0x85},
    {ADV7511_ADDR>>1, 0x2E, 0x18},
    {ADV7511_ADDR>>1, 0x2F, 0xBE},
#endif
    {ADV7511_ADDR>>1, 0x41, 0x10}, // Power down control
                                   //    R0x41[  6] = PowerDown = 0 (power-up)
    {ADV7511_ADDR>>1, 0x48, 0x08}, // Video Input Justification
                                   //    R0x48[8:7] = Video Input Justification = 01 (right justified)
    {ADV7511_ADDR>>1, 0x55, 0x00}, // Set RGB in AVinfo Frame
                                   //    R0x55[6:5] = Output Format = 00 (RGB)
    {ADV7511_ADDR>>1, 0x56, 0x28}, // Aspect Ratio
                                   //    R0x56[5:4] = Picture Aspect Ratio = 10 (16:9)
                                   //    R0x56[3:0] = Active Format Aspect Ratio = 1000 (Same as Aspect Ratio)
    {ADV7511_ADDR>>1, 0x98, 0x03}, // ADI Recommended Write
    {ADV7511_ADDR>>1, 0x9A, 0xE0}, // ADI Recommended Write
    {ADV7511_ADDR>>1, 0x9C, 0x30}, // PLL Filter R1 Value
    {ADV7511_ADDR>>1, 0x9D, 0x61}, // Set clock divide
    {ADV7511_ADDR>>1, 0xA2, 0xA4}, // ADI Recommended Write
    {ADV7511_ADDR>>1, 0xA3, 0xA4}, // ADI Recommended Write
    {ADV7511_ADDR>>1, 0xAF, 0x04}, // HDMI/DVI Modes
                                   //    R0xAF[  7] = HDCP Enable = 0 (HDCP disabled)
                                   //    R0xAF[  4] = Frame Encryption = 0 (Current frame NOT HDCP encrypted)
                                   //    R0xAF[3:2] = 01 (fixed)
                                   //    R0xAF[  1] = HDMI/DVI Mode Select = 0 (DVI Mode)
    //{ADV7511_ADDR>>1, 0xBA, 0x00}, // Programmable delay for input video clock = 000 = -1.2ns
    {ADV7511_ADDR>>1, 0xBA, 0x60}, // Programmable delay for input video clock = 011 = no delay
    {ADV7511_ADDR>>1, 0xE0, 0xD0}, // Must be set to 0xD0 for proper operation
    {ADV7511_ADDR>>1, 0xF9, 0x00}  // Fixed I2C Address (This should be set to a non-conflicting I2C address)
};

 

 

Screenshot from _vtc_dump.png
Screenshot from_vdma_dump.png
0 Kudos
Highlighted
Moderator
Moderator
2,597 Views
Registered: ‎11-09-2015

HI @aynilian,

 

Do you check the locked/undeflow/overflow signals from the AXI4-Stream to video out?

 

If you do not get the locked signal, it means the issue is inside the FPGA. Else this might be with the DP159. Can you check and report?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Moderator
Moderator
2,515 Views
Registered: ‎11-09-2015

Hi @aynilian,

Do you have any updates on this topic?


If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Explorer
Explorer
2,505 Views
Registered: ‎07-05-2017

Hi Florentw,

 

I do not get the locked signal when I am running in Petalinux build, but in Bare-metal build, sometimes the signal locks and puts out an HDMI image.

 

As far as the DP159 I am not sure which IP Core is that. Here is a snippet of my IP blocks to do VDMA Axi stream flow from DDR memory to HDMI port. The IP blocks are: VDMA core 6.3, Axi stream subset converter 1.1, RGB to YCrCb Color space converter 7.1, Video Timing Controller 6.1, Chroma Resampler 4.0, Axi Stream to Video Out 4.

 

Note: There are some active low resets that I have tied to VCC. At one point, I tied them to VIO and toggled them, but had no change in making the system work when it was not putting out anything and lock signal did not go active. I am still looking for other options on tying the  resets tied to VCC to a reset generator from the appropriate clock sources.

 

HDMI 2018-09-14 20-01-51.png

 

At one point, I stuck an ILA probe to the VDMA signals ( m_axis_mm2s_tready, m_axis_mm2s_tvalid..) and I did not see any activity when I was running in Petalinux build.  Even though the data dump of the registers indicated that the R/S bit in the control register was set and the ISR HALT bit was 0 as indicated in my previous correspondence.

 

Screenshot from 2018-09-14 20-27-48.png

My question is: Why the VDMA IP block that indicates proper R/S values not accessing the DDR memory as the  programmed pointer registers indicate that it should, and the Vertical Size register is written last to start the DMA?

 

0 Kudos
Highlighted
Moderator
Moderator
2,400 Views
Registered: ‎11-09-2015

HI @aynilian,

 

Sorry by DP159 I meant ADV7511... The DP159 is the chip use the the HDMI SS IP.

 


@aynilian wrote:

 

I do not get the locked signal when I am running in Petalinux build, but in Bare-metal build, sometimes the signal locks and puts out an HDMI image.

 


> You should try to have the locked signal always high. If it is sometimes, this means your pipeline is a bit unstable so the linux might only expose that issue every time.

 

 


@aynilian wrote:

At one point, I stuck an ILA probe to the VDMA signals ( m_axis_mm2s_tready, m_axis_mm2s_tvalid..) and I did not see any activity when I was running in Petalinux build.  Even though the data dump of the registers indicated that the R/S bit in the control register was set and the ISR HALT bit was 0 as indicated in my previous correspondence.

 

Screenshot from 2018-09-14 20-27-48.png

My question is: Why the VDMA IP block that indicates proper R/S values not accessing the DDR memory as the  programmed pointer registers indicate that it should, and the Vertical Size register is written last to start the DMA?

 


> Are you using the linux driver directly for the VDMA or are you trying to access it through devmem?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Explorer
Explorer
2,321 Views
Registered: ‎07-05-2017

Hi florent

 

I'm using the devmem virtual memory mapping method of mapping the physical address of the VDMA to the Virtual memory in Linux.

 

Thanks,

Armen.

0 Kudos
Highlighted
Moderator
Moderator
2,198 Views
Registered: ‎11-09-2015

HI @aynilian,

 

My recommendation is to go back to the baremetal driver and make sure you can reliably get a video on the display, not sometimes


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Explorer
Explorer
2,190 Views
Registered: ‎07-05-2017

Hi Florent,

 

I will strip out my design and just leave the HDMI / VDMA blocks in. See if the Baremetal is stable all the time under all power up and reset conditions and then build the Linux Kernel.

 

Thanks,

Aynilian

0 Kudos
Highlighted
Moderator
Moderator
2,151 Views
Registered: ‎11-09-2015

Hi @aynilian,

 

Do you have any updates on this?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Explorer
Explorer
2,134 Views
Registered: ‎07-05-2017

Hi Florent,

 

While isolating the VDMA and Chroma Re-sampler, my evaluation license ran out. So I am trying to figure out how to get another extension for the Evaluation license for the above mentioned cores. I tried renewing it, but Xilinx give me a message that I have already generated an eval license for this host.  I wonder if there are alternative ways of streaming data to the HDMI chip (maybe use CDMA and write into a FIFO).

 2018-10-09_1543.png

 

Thanks,

Aynilian

0 Kudos
Highlighted
Moderator
Moderator
2,125 Views
Registered: ‎11-09-2015

HI @aynilian,

 

You can use only the VDMA for the moment. I do not think it requires a license. You might have wrong color but at least it might be a good start if you can get an output.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Explorer
Explorer
2,111 Views
Registered: ‎07-05-2017

Hi Florent,

 

I took out the Chroma Re-sampler and connected the Vid_io_out [23:0] from the "Axi4 Stream to Video Out" block to the hdmi output that is 16 bits wide. The Chroma -Resampler was taking care of the video width conversion before. In any case the good news is that I can generate Bitstream now. 

 

I put in ILA blocks on the input and output of the VDMA block. And I do see that the VDMA at least runs, but I did see a few times that it had stopped running, where I had to re-load the FPGA bitstream. 

 

The ILAs showing while the VDMA is running but the "locked" bit out of the "Axi4 Stream to Video Out" block is low. The "underflow" signal is toggling up and down. This tells that the data is going in slower than coming out.

 

I will try to gut the design now and see if the  "locked" bit is stable and high all the time. Then go from there and create a Petalinux project.

 

Thanks

Aynilian

 

Highlighted
Explorer
Explorer
2,012 Views
Registered: ‎07-05-2017

axi_vdma_MM2S_ILA.png

Here Was the Original Designs

 

1. Gutted the Design to just include the VDMA and supporting blocks

 

hdmi_only_with_ILA.png

Here is the stripped down design

 

2. Ported the stripped down FPGA to Petalinux and found couple of VTC registers that did not match the original bare metal. Corrected it.

vtc_bare_metal.png

 

Bare Metal VTC Register Dump

 

 

VTC_Linux_Reg_update.png

Linux VTC Register Dump after update

 

Good News!

 

3. After the modifications to the code in petalinux, I could see that the "Lock Bit" was solid high and no fluctuations on the underflow. (good News!). VDM running and streaming out Video out data. Now the problem is the Display. Even though I can see a Display,  There are a lot of dark horizontal lines in the image. Something is off compared to the Bare Metal. Seems like a video timing problem

 

I will dig in more check if there are any more differences between the HDMI IIC ADV7511 chip configuration between the bare metal and the Petalinux version, since I had done bunch of porting of the code to Petalinux, I may have missed something.

 

Will Let you Posted.

 

Thanks,

Aynilian

 

 

 

 

 

Highlighted
Explorer
Explorer
2,011 Views
Registered: ‎07-05-2017

Hi

 

Okay, I fixed the display timing issue. Had a wrong valud in GEN_F0_VSYNC_V VTC register at location 0xxxxx_0080

 

Modified code as shown below.

 *(uBaseAddr+GEN_F0_VSYNC_V_OFFSET) = 0X0441043C;  //GEN_F0_VSYNC_V

 

The HDMI Display looks good with the Color bars in Petalinux.

 

Now I will start adding my Design and see when things deteriorate. I will try to lock the placement and create multiple runs based on this reference design.

 

Will keep you posted when the full design works.

 

Thanks

Aynilian

 

 

Highlighted
Moderator
Moderator
2,177 Views
Registered: ‎11-09-2015

HI @aynilian,

 

Thank you for sharing your findings with the community. I am sure this can be helpful for another member ;)

 

Let me know if you are facing issues in the next steps and please share your final results :)

 

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post