03-11-2014 10:57 AM
I have some question about applying and checking clock timing constraints in System Generator IP Core in EDK Design.
We use SysGen IP Core inside big EDK System with Microblaze, Axi Lite, and PCIe Endpoint. Device is Virtex-6.
The problem is that our SysGen Design works inproperly from synthesis to synthesis - e.g sometimes already tested blocks stop working or one instance of the same block is working improperly when others are OK. So we suggest that some timing constraints for SysGen design are missing.
The clock for Sysgen is generated from Clock Generator Pcore in EDK, which creates from external 200MHz differential signal on clock pins 100MHz for SysGen.
Sysgen also has Axi Clock coming from another port of the same clock Generator.
So the first question about this - we have checked Timing report after Place and Route and found, that for all constraints which were created for 200Mhz or 100Mhz clock signals, the Timing report shows 0 analyzed paths. At the same time we are sure, that our complex Sysgen Design contains at least several tens of millions paths (we know from previous designs). We also found, that if we purposely create complex signal path in Sysgen without pipeline registers - no timing error generated.
So the question - should Timing Report show covered SysGen design Paths or not? If not, where they are checked? Does Sysgen on IP Core Export generate timing constraints automatically and will be they applied by EDK automatically?
03-12-2014 02:34 PM
03-15-2014 10:21 AM