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Registered: ‎08-20-2007

Applying Clock Timing Constraint to System Generator IP Core

Dear Community.

I have some question about applying and checking clock timing constraints in System Generator IP Core in EDK Design.

We use SysGen IP Core inside big EDK System with Microblaze, Axi Lite, and PCIe Endpoint. Device is Virtex-6.


The problem is that our SysGen Design works inproperly from synthesis to synthesis - e.g sometimes already tested blocks stop working or one instance of the same block is working improperly when others are OK. So we suggest that some timing constraints  for SysGen design are missing.


The clock for Sysgen is generated from Clock Generator Pcore in EDK, which creates from external 200MHz differential signal on clock pins 100MHz for SysGen.


Sysgen also has Axi Clock coming from another port of the same clock Generator.


So the first question about this - we have checked Timing report after Place and Route and found, that for all constraints which were created for 200Mhz or 100Mhz clock signals, the Timing report shows 0 analyzed paths. At the same time we are sure, that our complex Sysgen Design contains at least several tens of millions paths (we know from previous designs). We also found, that if we purposely create complex signal path in Sysgen without pipeline registers - no timing error generated.


So the question - should Timing Report show covered SysGen design Paths or not? If not, where they are checked? Does Sysgen on IP Core Export generate timing constraints automatically and will be they applied by EDK automatically?


Thank you.


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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2011

Do you have a period constraint on your incoming 200MHz clock? As long as this has a proper constraint, the tools can figure out the downstream constraints from the Clock Generator and should apply them for you.

You might want to also check the constraint interaction report to make sure that no other constraint is accidentally taking precedence over the period.
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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2008

When System Generator for DSP generates the HDL Netlist for a model it creates a file called modelname_cw.xcf. This is the synthesis constraints file used by XST. These constraints are then passed on to the implementation tools via the netlist.

System Generator will write out several different timing constraints automatically depending on your design.

First System Generator for DSP will always write out a single Global period constraint. For models that contain additional clock domains, a multi-cycle FROM/TO constraint will be written out for each additional sample rate domain, FROM all elements a given CE drives TO all elements that same CE drives.

In addition to the multi-cycle FROM/TO timing constraints, cross-clock domain, group-to-group constraints will also be written. System Generator for DSP writes out constraints for all possible combinations between each CE time group. It is possible that there may be many more FROM/TO or Group-to-group constraints listed than are actually used in the design. The constraints that are not being used will be empty during timing analysis in PAR.

Here is an Example:

# Global period constraint

NET "clk" TNM_NET = "clk_b97b17b0";

TIMESPEC "TS_clk_b97b17b0" = PERIOD "clk_b97b17b0" 50.0 ns HIGH 50 %;

# ce_2_b97b17b0_group and inner group constraint

Net "ce_2_sg_x0*" TNM_NET = "ce_2_b97b17b0_group";

TIMESPEC "TS_ce_2_b97b17b0_group_to_ce_2_b97b17b0_group" = FROM "ce_2_b97b17b0_group" TO "ce_2_b97b17b0_group" 100.0 ns;

# ce_40_b97b17b0_group and inner group constraint

Net "ce_40_sg_x0*" TNM_NET = "ce_40_b97b17b0_group";

TIMESPEC "TS_ce_40_b97b17b0_group_to_ce_40_b97b17b0_group" = FROM "ce_40_b97b17b0_group" TO "ce_40_b97b17b0_group" 2.0 us;

# Group-to-group constraints

TIMESPEC "TS_ce_2_b97b17b0_group_to_ce_40_b97b17b0_group" = FROM "ce_2_b97b17b0_group" TO "ce_40_b97b17b0_group" 100.0 ns;

TIMESPEC "TS_ce_40_b97b17b0_group_to_ce_2_b97b17b0_group" = FROM "ce_40_b97b17b0_group" TO "ce_2_b97b17b0_group" 100.0 ns;

For further assistance regarding the constraints syntax, refer to the Development System Reference Guide and Constraints Guide in the Software Manuals.
Thanks and Regards
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