cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Observer
Observer
1,120 Views
Registered: ‎05-08-2018

[Artix 7] Create the pattern to test VDMA using loopback

Jump to solution

Hi, 

I'm learning how to use DMA, VDMA. So I choose the loopback mode to verify them and I need to make the pattern. In Dma, I easily create the pattern to test transmit in loopback mode, I just need to make to for loop to put the pattern into Tx Buffer. My pattern includes two packets, each packet has the 8-bit length like this: 

//MAX_PK_LENGTH = 8 bit
for (Index = 0; Index < 2*MAX_PK_LENGTH; Index++){
		*(TxBufferPtr+Index) = Value;
		xil_printf ("TX addr: %x  and value: %x\n\r", (unsigned int)(TxBufferPtr+Index),(unsigned int)TxBufferPtr[Index]);
		Value = (Value+1) & 0xFF;
And this way to verify: 
for (Index = 0; Index < 2*MAX_PK_LENGTH; Index++){
		if (RxBufferPtr[Index] != Value){
			xil_printf("Data error %d: %x/%x\r\n",
						    Index, (unsigned int)RxBufferPtr[Index],
						    (unsigned int)Value);
		}
		xil_printf ("RX addr: %x  and value: %x \n\r", (unsigned int)(RxBufferPtr+Index),(unsigned int)RxBufferPtr[Index]);
		Value = (Value+1) & 0xFF;
	}
 And in VDMA, I use frame video: 640x480 (1 pixel = 4 bytes). It means each frame(packet) is 0x12C000 bytes, and I don't know how to create like that frame because it 's too large to create the pattern by for loop and test. Any suggestions to create the pattern to verify in VDMA ? 
Capture3.PNG
And if I use Test pattern generator, can I use the diagram below to verify loopback in VDMA? (As compare buf_0 with buf_1 after transmit done)
Untitled.png
 
Tags (2)
0 Kudos
Reply
1 Solution

Accepted Solutions
Moderator
Moderator
1,030 Views
Registered: ‎11-09-2015

Hi @skyfall133,

 

The Test Pattern Generator as an example design you can use.

 

I also wrote the Video Beginner Series 4 showing the TPG IP in simulation.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

4 Replies
Moderator
Moderator
1,067 Views
Registered: ‎11-09-2015

Hi @skyfall133,

 

I would use the solution with the VDMA, this is the easiest way for me. Yes you should be able to do as per your suggestion.

 

Let me know if you have any issue doing this.

 

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Observer
Observer
1,033 Views
Registered: ‎05-08-2018

@florentw thanks for the reply, 

I am doing that. If I have any issue, I will tell you. 

By the way, where can I find some tutorial/source code to learn how to use test pattern generation? 
 
 
0 Kudos
Reply
Moderator
Moderator
1,031 Views
Registered: ‎11-09-2015

Hi @skyfall133,

 

The Test Pattern Generator as an example design you can use.

 

I also wrote the Video Beginner Series 4 showing the TPG IP in simulation.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Moderator
Moderator
973 Views
Registered: ‎11-09-2015

HI @skyfall133,

Do you have any update on this?

If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply