cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
zoechen
Observer
Observer
834 Views
Registered: ‎08-27-2019

Axi4-Stream to Video not work in HDMI RX only example.

Hi all ,

I am trying hdmi rx only example which add IP axi4-stream to video out  to convert axi stream to video stream with board ZCU106 .(The complete block diagram is in the attachment)

diagram.png

I have checked my v_tc's (Video Timing Controller) output is correct and Axi4-Stream to Video Out's inputs video_in have some data stream in.

But this ip still not work . My locked signal is zero ,and vid_io_out signals are all Zeros.

locked.png

How can I make this IP works?

Many Thanks.

 

 

0 Kudos
9 Replies
watari
Teacher
Teacher
783 Views
Registered: ‎06-16-2013

Hi @zoechen 

 

Is your issue occured on simulation ? or ZCU106 ?

If on ZCU106, would you make sure EDID ?

Also, what kind of source device are you using ?

 

Best regards,

0 Kudos
zoechen
Observer
Observer
753 Views
Registered: ‎08-27-2019

Hi @watari 

Thanks for your reply.

Is your issue occured on simulation ? or ZCU106 ?

This issue occured on ZCU106.

If on ZCU106, would you make sure EDID ?

I don't know how to make sure my EDID...

Also, what kind of source device are you using ?

My vedio source is my pc ,and it's resolution is 1920x1080.

 

Also I have some IP setting picture below.

v_tc_1v_tc_1v_tc_2v_tc_2v_tc_3v_tc_3axi4-stream_to_videoaxi4-stream_to_video

Many Thanks!

Zoechen

 

0 Kudos
watari
Teacher
Teacher
748 Views
Registered: ‎06-16-2013

Hi @zoechen 

 

I'm sure that it's EDID issue.

Is your design for barematal ?

If yes, you must prepare proper EDID.

If no and you use petalinux, make sure log message by HDMI Rx kernel driver.

 

Best regards,

florentw
Moderator
Moderator
689 Views
Registered: ‎11-09-2015

HI @zoechen 

In your ILA this is quite clear that you have an underflow issue.

You might want to consider adding an AXI VDMA or Video Frame buffer Read/Write to buffer the Video Stream. This is what will be done in most video design.

Else, make sure the clock you are using is correct and use a FIFO (I would still recommend the fist option)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
ashokkum
Moderator
Moderator
665 Views
Registered: ‎04-09-2019

Hello @zoechen ,

As mentioned by @florentw , Underflow is the main cause for this Issue. I hope this underflow issue would be arise,  because of  the source EDID or the pixel clock Issue. Could You please share the UART log of this design with us. So,That we will get to know about the training status of the links.

Also, If possible could You please try with some other HDMI sources like Nvidia shield etc., and share the UART log of this test also with us. The UART log's will help us more to debug on this issue.

With Regards,

Ashok

0 Kudos
zoechen
Observer
Observer
645 Views
Registered: ‎08-27-2019

Hi @florentw ,

Thanks for your reply.

Because I use existing HDMI RxOnly example code, and the IP Video Frame buffer Write have input pin called s_axi_CTRL  ,I don't have any idea about how to connect it.Or can I just tie this a constant?

I have checked my clocks,but I don't understand what this "use a FIFO (I would still recommend the fist option)" means.

 

Many thanks ,

Zoechen

0 Kudos
zoechen
Observer
Observer
640 Views
Registered: ‎08-27-2019

Hi @ashokkum ,

Thanks for your reply.

I have some screenshot below.

And I will trying find another HDMI source to test .

info1.pnginfo2.pnginfo3.png

Many thanks,

Zoechen

0 Kudos
florentw
Moderator
Moderator
633 Views
Registered: ‎11-09-2015

HI @zoechen 

s_axi_CTRL is the AXI4-Lite interface used to program the Video Frame buffer. It has to be connected to the processor. Then you will have to add the code to set up the video frame buffer


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
florentw
Moderator
Moderator
553 Views
Registered: ‎11-09-2015

Hi @zoechen 

Did you make any progress on this?

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos