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Observer
Observer
1,202 Views
Registered: ‎05-16-2018

Beginner Series 3 source files issue with Verilog build script

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In the Beginner Series 3 code I am unable to successfully source the build verilog TCL in Vivado 2018.1 (I have also tried in 2018.2 with same result).

 

I get a critical warning 

[filemgmt 20-2001] Source scanning failed (launch error) while processing fileset "sim_1" due to unrecoverable syntax error or design hierarchy issues. Recovering last known analysis of the source files.

 

The project looks like this 

vivado_build_error.png

 

I have read that when you import the verilog source it will be classified as Non-module files if there is a compile problem. 

Check-syntax does not indicate any error with the fileset.

check_syntax
INFO: [Vivado 12-4796] No errors or warning reported.
check_syntax -fileset sim_1
INFO: [Vivado 12-4796] No errors or warning reported.

 

Attempting to run the simulation the tool will ask for a valid top module name.  It appears I do not have one.

 

Any suggestion to help me get going?  I think the VHDL version would work, but I would like to keep my environment in Verilog, as all my other code is in Verilog.

 

Thanks!

 

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Moderator
Moderator
1,171 Views
Registered: ‎06-14-2010

Hello @briankincaid,

 

This perhaps be related to an HSV/srcscanner issue, where scrscanner (HSV2.0) is having trouble running. I will send you privately some things to try out, that may be able to help you with this issue. I don't want to share this publicly, as this is wasn't tested fully and may not work for all users.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @briankincaid,

 

Did you made any modification to the verilog file?

 

I tried again the script and asked a colleague to try and it was successful in both cases (with different machine and OS)

 

I assume you already went through a first simulation as you have image_3.ppm already in your sources files. Is it correct?

 

Regards,

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
1,172 Views
Registered: ‎06-14-2010

Hello @briankincaid,

 

This perhaps be related to an HSV/srcscanner issue, where scrscanner (HSV2.0) is having trouble running. I will send you privately some things to try out, that may be able to help you with this issue. I don't want to share this publicly, as this is wasn't tested fully and may not work for all users.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
-------------------------------------------------------------------------
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Observer
Observer
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Registered: ‎05-16-2018

Florent, 

I tried unmodified, and also attempted to modify the tcl file but have the same result either way.

 

I did not go through the previous simulation.  I built this as a new project with your source.  I am using a fresh 2018.1 install. 

I pulled the image_2 and image_3 files from the .zip and added them as sources.

 

Anatoli sent me some things to try so I will try those.  I am running on Windows 10 64b (home) 

 

Best regards,

Brian (Daniel) Kincaid

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