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Visitor
Visitor
7,391 Views
Registered: ‎10-15-2007

Bi-directional pins: how to configure them in system generator?

Hi all,

 

I want to use a set of FPGA pins as bi-directional I/Os together with System Generator. How can I do this? How do I configure my target hardware for this?

 

Best regards,


Sergio Rui Silva

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Xilinx Employee
Xilinx Employee
7,390 Views
Registered: ‎08-07-2007

bi-directional Gateways are not currently availble in System Generator.  Inputs and outputs should be treated seperately and once the HDL is generated a bi-directional port can be created at the top level to route these through a single IO.  Take a look at answer record 15505 for more details:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=15505

Another possibility is to attempt to bring in a bi-directional IO buffer with an HDL black box, however the former is the recommended flow.
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Visitor
Visitor
7,336 Views
Registered: ‎11-09-2007

Hi jeffreyh,

I have the same Problem, but please give me a detailed, beginner-friendly explanation of howto "bring in a bi-directional IO buffer with an HDL black box" . Which files need to be changed? and how?
(EDK 8.1i)

Thank you



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Visitor
Visitor
7,107 Views
Registered: ‎03-15-2008

i have a similar problem .... but i want to change the sample time of my output of black box... how should i do it ?....
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