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ryant
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Registered: ‎10-29-2020

CLB count to enable MIPI DPHY on Ultrascale+

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Hi,

I'd like to know how much CLB will be consumed when enabling and integrating MIPI DPHY on Ultrascale+ FPGA? The FPGA system will only has MIPI DSI, no CSI. MIPI host controller gate count and CPU core gate count will be estimated at my end. Preferably, I'd like to get the maximum gate count, up to to dual channels of 4 MIPI lanes each.

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florentw
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Registered: ‎11-09-2015

HI @ryant 

If you check the IP facts table on the pg202 you will see a link to the Resource Utilization for MIPI D-PHY v4.2:

MIPI.JPG

If you need more then just add the D-PHY 2 IPs to a design and run synthesis. This will give you the estimate


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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florentw
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Registered: ‎11-09-2015

HI @ryant 

If you check the IP facts table on the pg202 you will see a link to the Resource Utilization for MIPI D-PHY v4.2:

MIPI.JPG

If you need more then just add the D-PHY 2 IPs to a design and run synthesis. This will give you the estimate


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

florentw
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134 Views
Registered: ‎11-09-2015

HI @ryant 

Is everything clear for you on this topic?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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