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tim_severance
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Registered: ‎03-03-2017

CSI-2 Example Project errors after changing CSI pins

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Hi, I was able to successfully use Vivado 2019.1 to implement the CSI-2 RX example design.   But in order to interface with some custom FMC hardware we have I had to update the CSI IP to use different pins on the FPGA (see below image 1 for my pin update).   I understand these are not the recommended sequential I/O, but the IP dialog does not say it is required and this is how our current hardware was laid out unfortunately.

Image 1:

foo1.png

   My problem comes in when I try to implement this design.   When I do I get the critical warnings and errors shown below in image 2.   These errors do not show when I use the default example project pins.

Image 2:

foo2.png

 

   Any ideas how to proceed from here?   I am not sure what the "bg3_pin6_nc" pin is used for or where I can re-assign it.

 

Thanks.

Tim

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karnanl
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Registered: ‎03-30-2016

Hello @tim_severance 

I have 2 questions. Could you please clarify ?
1. Did you connect "bg3_pin6_nc" port to top layer if your design ? 
2. Did you assign "bg3_pin6_nc" pin in Y2 pin ? Can you please share your XDC ?

Regards
Leo

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florentw
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Hi Tim @tim_severance 

When you use non-aligned IOs, you might end up with IOs your need to burn (i.e. you will not be able to use for anything else).

So if you are using this pin for anything else in your design, then you will face issue.

Thus bg3_pin6_nc needs to be located to Y2 as burn IO so you cannot use pin Y2 in your design. Can you confirm you are not using it? If not, could you share the xci file for your MIPI IP?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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tim_severance
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@florentw ,

   Correct, I am not using this for anything else in the design.

   The XCI file is attached.

Thanks.

Tim

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tim_severance
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@florentw ,

   When PG202 says the DSI RX "left out IO cannot be used by any other design and it will be unusable", can you explain a little?   For the CSI RX I am wanting to use bank 66 L16/QBC for the clock, L19, L20, L15, and L24 for the 4 lanes.   Does this mean that all bank 66 L1..L14, L17..L18, L19, L21..L23 are all unusable?   Or does this refer to the byte section pins within the same byte sections?

Thanks.

Tim

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tim_severance
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@florentw ,

   I just realized the example design is setup to use LI-IMX274MIPI-FMC Camera Sensor Module which I am not using.   I will need to look through the block design.   Chances are that pin is being used for something on that FMC board.

   Although on the original implementation of the example design as-is, the Y2 pin did not show as being used for anything when looking at the IO connections.   I don't have access to a schematic for this module to see if that pin is used for something.

Tim

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tim_severance
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@florentw ,

   If I open the OPT checkpoint and do a get_ports in the tcl console I get the list below.   So there is likely a bug somewhere since the xdc is calling for a bunch of "get_ports" that don't exist.

 

get_ports:

GPIO_sensor_tri_o[0]
GPIO_sensor_tri_o[1]
GPIO_sensor_tri_o[2]
HDMI_TX_CLK_N_OUT
HDMI_TX_CLK_P_OUT
HDMI_TX_DAT_N_OUT[0]
HDMI_TX_DAT_N_OUT[1]
HDMI_TX_DAT_N_OUT[2]
HDMI_TX_DAT_P_OUT[0]
HDMI_TX_DAT_P_OUT[1]
HDMI_TX_DAT_P_OUT[2]
IIC_sensor_scl_io
IIC_sensor_sda_io
LED0
SI5324_LOL_IN
SI5324_RST_OUT[0]
TX_DDC_OUT_scl_io
TX_DDC_OUT_sda_io
TX_EN_OUT[0]
TX_HPD_IN
TX_REFCLK_N_IN
TX_REFCLK_P_IN
fmch_iic_scl_io
fmch_iic_sda_io
gpio_display_tri_o[0]
gpio_display_tri_o[1]
mipi_phy_csi_clk_n
mipi_phy_csi_clk_p
mipi_phy_csi_data_n[0]
mipi_phy_csi_data_n[1]
mipi_phy_csi_data_n[2]
mipi_phy_csi_data_n[3]
mipi_phy_csi_data_p[0]
mipi_phy_csi_data_p[1]
mipi_phy_csi_data_p[2]
mipi_phy_csi_data_p[3]
mipi_phy_dsi_clk_n
mipi_phy_dsi_clk_p
mipi_phy_dsi_data_n[0]
mipi_phy_dsi_data_n[1]
mipi_phy_dsi_data_n[2]
mipi_phy_dsi_data_n[3]
mipi_phy_dsi_data_p[0]
mipi_phy_dsi_data_p[1]
mipi_phy_dsi_data_p[2]
mipi_phy_dsi_data_p[3]
reset
sys_diff_clock_clk_n
sys_diff_clock_clk_p

Tim

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karnanl
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Registered: ‎03-30-2016

Hello @tim_severance 

I have 2 questions. Could you please clarify ?
1. Did you connect "bg3_pin6_nc" port to top layer if your design ? 
2. Did you assign "bg3_pin6_nc" pin in Y2 pin ? Can you please share your XDC ?

Regards
Leo

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tim_severance
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@karnanl ,

   Funny, right when you responded I realized there might be a connection added in the block design that needed to be connected after I made the pin change.   Indeed you are correct, there is now a pin called bg3_pin6_nc which I did not connect.   I guess I was surprised it didn't cause a validation error.

   I connected it and am about to try to implement and will update this forum post with my results.

Thanks.

Tim

tim_severance
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@karnanl ,

   I made the connection to the new pin in the Block Design and added it to the top level and then it implemented and bitstream wrote successfully!

Thanks!

Tim