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Registered: ‎03-03-2017

CSI-2 RX Line Rate by device

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Is there a document available that shows what devices support what maximum CSI-RX line rates?

For instance I started an Artix-7 project (AC701 board), and when setting up the CSI-RX the highest line rate supported is 1360Mbps.   I can't seem to find this documented by Xilinx anywhere.   

I need this so I can determine what device we need to use in our application.

Thanks.

Tim

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Tim @tim_severance 

I believe @florentw  already answered all of your questions.
Just adding a few things.

>For instance I started an Artix-7 project (AC701 board), and when setting up the CSI-RX the highest line rate supported is 1360Mbps

This is not correct.
It should be 1250Mbps at max as @florentw  mentioned

Artix-7, like other 7-series devices do not have a native support MIPI D-PHY,
So if you are using MIPI IP with 7-series device, you need to use an external components to convert LVDS to MIPI signals ( and vice versa). XAPP894 shares the concept of how to implement the external component.
For a cost-critical system with a typical MIPI D-PHY signal level, some users will opt to use an external resistor network. I would suggest doing board simulation with IO IBIS model to ensure that resistor network can be used to receive signal from your TX/sensor.
To achieve 1250Mbps with 7-series devices, external PHY device usage (i.e Meticom) is necessary.

===

FPGAs that support
2.5Gbps CSI-2-RX : UltraScale+ Kintex, UltraScale+ MPSoC
2.0Gbps CSI-2-RX : UltraScale+ Kintex, UltraScale+ MPSoC
1.5Gbps CSI-2-RX : UltraScale+ Kintex, UltraScale+ MPSoC, UltraScale+ Virtex

(*) Note :
UltraScale+ RFSoC and ACAP Versal devices also have the capability to support MIPI D-PHY natively using its IO but I think it is overkill if you do not intend to use the device special features.

Definitely, you will need to use UltraScale+ devices to achieve 2.5Gbpps MIPI.

Kind regards
Leo

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Registered: ‎11-09-2015

Hi @tim_severance 

The line rate limitation usually comes from the device. So you might find some information in the pg202 but ultimately the ultimately answer will be in the datasheet for the device you are using


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎03-03-2017

@florentw ,

   I looked through the artix-7 datasheet (DS181)  and did a text search for 1360 and nothing showed up.

   Do you know what spec in the datasheet is the one I need to look at?

Tim

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Registered: ‎03-03-2017

@florentw ,

   In case documentation does not exist, could you possibly give me 3 lists:

  1. FPGAs that support 2.5Gbps CSI-2-RX
  2. FPGAs that support 2.0Gbps CSI-2-RX
  3. FPGAs that support 1.5Gbps CSI-2-RX

Thanks

Tim

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Registered: ‎11-09-2015

Hi @tim_severance 

It seems to be an issue with the MIPI CSI-2 GUI. The datasheet should be the main reference.

Also the MIPI D-PHY IP seems to be correct. The maximum line rate for Artix-7 should be 950 for -1 and 1250 for -2 and -3

I will report this to development


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎03-03-2017

@florentw ,

   Can you please confirm that the spec that shows 1250Mbps actually means 2500Mbps CSI-RX?   I figure this must be the case because the same spec on the Zynq Ultrascale+ device I am currently using also shows 1250 and I have it running CSI RX at 2.5Gbps.

Thanks.

Tim

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Registered: ‎11-09-2015

Hi @tim_severance 

This is mentioned in the latest version of the datasheet DS925:MIPI.JPG

make sure you are always looking at the latest version of the doc. I would recommend using docnav.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎03-03-2017

@florentw ,

   Ok, this helps with the Zynq UltraScale+, but I am wanting to see what the Artix and Kintex devices can do, and in the Artix datasheet I do not see any section regarding MIPI DPHY Performance.

   For the datasheets without the DPHY Performance specs I should simply rely on the DDR LVDS receiver spec?   If so then it appears the Zynq Ultrascale+ is the only device that supports 2.5Gbps.   It would be helpful if this were spelled out somewhere so a CSI RX user would know what device would be required should they want to use the 2.5Gbps.

   Thanks for any inputs here.

Tim

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Tim @tim_severance 

I believe @florentw  already answered all of your questions.
Just adding a few things.

>For instance I started an Artix-7 project (AC701 board), and when setting up the CSI-RX the highest line rate supported is 1360Mbps

This is not correct.
It should be 1250Mbps at max as @florentw  mentioned

Artix-7, like other 7-series devices do not have a native support MIPI D-PHY,
So if you are using MIPI IP with 7-series device, you need to use an external components to convert LVDS to MIPI signals ( and vice versa). XAPP894 shares the concept of how to implement the external component.
For a cost-critical system with a typical MIPI D-PHY signal level, some users will opt to use an external resistor network. I would suggest doing board simulation with IO IBIS model to ensure that resistor network can be used to receive signal from your TX/sensor.
To achieve 1250Mbps with 7-series devices, external PHY device usage (i.e Meticom) is necessary.

===

FPGAs that support
2.5Gbps CSI-2-RX : UltraScale+ Kintex, UltraScale+ MPSoC
2.0Gbps CSI-2-RX : UltraScale+ Kintex, UltraScale+ MPSoC
1.5Gbps CSI-2-RX : UltraScale+ Kintex, UltraScale+ MPSoC, UltraScale+ Virtex

(*) Note :
UltraScale+ RFSoC and ACAP Versal devices also have the capability to support MIPI D-PHY natively using its IO but I think it is overkill if you do not intend to use the device special features.

Definitely, you will need to use UltraScale+ devices to achieve 2.5Gbpps MIPI.

Kind regards
Leo

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Registered: ‎03-03-2017

@karnanl Thank you for the detailed description.   I think I am starting to understand what devices have what capabilities for MIPI CSI.   
One more question.    What is your lowest entry cost UltraScale+ device?    If we were to use it in our application we need it to not be too expensive.   Our current application uses an Artix-7 device.   I realize you probably don’t have any UltraScale+ devices in that price range though.  
Thanks.  
Tim

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @tim_severance 

Please contact your FAE for this type of information. We do not have any pricing information in technical support.

And this will all depends on multiple parameters.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎03-03-2017

@florentw ,

   Ok, I understand this isn't the right forum to discuss pricing.

   I have a question though.   I notice (some of) the Zynq UltraScale+ devices are in the same price range as the Artix-7 devices we currently use.   Can you point me to who can help me understand why I may not want to use a Zynq ultrascale+ device coming from an Artix-7?   I understand there is a uProcessor built in, but I wouldn't have to use it.   I would mainly use the chip for the addition of the built in MIPI circuitry.

Thanks.

Tim

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Registered: ‎11-09-2015

Hi @tim_severance 

If you have a Zynq Ultrascale+ for the same price as a Artix-7 then I would say go for it with no hesitation. I would not see any reason why you would stick with an Artix-7 if not for the price.

There is a built-in processor but you were probably having a microblaze in your design so it is just better.

For MIPI, you do not need the external PHY so I would reduce the cost of you PCB...

I try to be nice with Artix-7 but I cannot help him on this case.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**