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Registered: ‎10-10-2017

CSI-2 RX constraints and configuration issues w/ IWR1443

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Hello,

as explained in the https://forums.xilinx.com/t5/Other-FPGA-Architecture/ADC-Data-LVDS-Deserialization-and-Axi-Stream/td-p/1068874#M37945 post, I am currently interfacing a Texas Instruments IWR1443 radar with a FPGA "xc7z030sbg485-1" (Zynq), in particular ZYNQ-7 TE0715_04_30_1I. SPRT PCB: REV04 from Trenz Electronic gmbh.

I need 4 data lanes, and we are using Vivado 2017.1

I am not sure I have a good grasp of the necessities of the MIPI CSI2 RX subsystem.

The CSI-2 RX subsystem has two sets of clock ports and data ports, one for High Speed and one for Low Power mode. On page 50 of the IWR1443 datasheet it says "the HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode".

1. Does it mean that I should physically connect ONLY the 4 differential HS pins for the data plus only the differential HS clock, because the other operating mode is not actually in use?

2. the RX subsystem has an Axi-Lite line for configuration, if I am not wrong. Should I pilot and configure the unit from my C code inside the microcontroller at startup? I do not see a register map in pg232, so I am sure I must be missing something.

thanks,

Michele Marconi

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: CSI-2 RX constraints and configuration issues w/ IWR1443

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Hello Michele @cloudscraper-86 

Your question is Video related. It should be posted on Video board not "Serial Transceivers" board.
https://forums.xilinx.com/t5/Video/bd-p/DSPTOOL

1. Does it mean that I should physically connect ONLY the 4 differential HS pins for the data plus only the differential HS clock, because the other operating mode is not actually in use?

No, this will not work. Connecting Low-power mode clock is a mandatory.

Unfortunately, Xilinx 7-series device (including ZYNQ-7000 that you are using) does NOT support MIPI D-PHY interface natively. You will need to use external chip-device or resistor network.
This XAPP may give you details information about it.
https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf

Anyway my sugesstion would be :
  (a) Using external PHY device from Meticom. (if your project requires ZYNQ-7000)
  (b) Using US+ MPSoC (instead of ZYNQ-7000), since UltraScale+ devices can support MIPI D-PHY interface.

2. the RX subsystem has an Axi-Lite line for configuration, if I am not wrong. Should I pilot and configure the unit from my C code inside the microcontroller at startup? I do not see a register map in pg232, so I am sure I must be missing something.


Please check PG232 Chapter2 (Page21-37) for register map
https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_rx_subsystem/v4_1/pg232-mipi-csi2-rx.pdf


Regards
Leo

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: CSI-2 RX constraints and configuration issues w/ IWR1443

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Hello Michele @cloudscraper-86 

Your question is Video related. It should be posted on Video board not "Serial Transceivers" board.
https://forums.xilinx.com/t5/Video/bd-p/DSPTOOL

1. Does it mean that I should physically connect ONLY the 4 differential HS pins for the data plus only the differential HS clock, because the other operating mode is not actually in use?

No, this will not work. Connecting Low-power mode clock is a mandatory.

Unfortunately, Xilinx 7-series device (including ZYNQ-7000 that you are using) does NOT support MIPI D-PHY interface natively. You will need to use external chip-device or resistor network.
This XAPP may give you details information about it.
https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf

Anyway my sugesstion would be :
  (a) Using external PHY device from Meticom. (if your project requires ZYNQ-7000)
  (b) Using US+ MPSoC (instead of ZYNQ-7000), since UltraScale+ devices can support MIPI D-PHY interface.

2. the RX subsystem has an Axi-Lite line for configuration, if I am not wrong. Should I pilot and configure the unit from my C code inside the microcontroller at startup? I do not see a register map in pg232, so I am sure I must be missing something.


Please check PG232 Chapter2 (Page21-37) for register map
https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_rx_subsystem/v4_1/pg232-mipi-csi2-rx.pdf


Regards
Leo

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Registered: ‎10-10-2017

Re: CSI-2 RX constraints and configuration issues w/ IWR1443

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Hello, and thank you for the detailed explanation.

Can you move the topic to the appropriate section without deleting it, maybe?


Regarding the external PHY device, is this (http://www.meticom.com/page2/page17/MC20901.html) what I should use? I have 4 data lanes coming from the A/D converter, that seems like the component I need
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: CSI-2 RX constraints and configuration issues w/ IWR1443

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Hello

1. Your post already moved by a kind moderator :- )

2. I think MC20901 can fit your use case since you only need 600Mbps.

 

 

Thanks & regards
Leo

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