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Adventurer
Adventurer
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Registered: ‎01-19-2018

CSI 2 Tx in Pass-Through

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CSI-2 TX Status:
-------------
Core Enable:                1
Soft Reset:                   0
Controller Ready:         1
ULPS Entry:                 0
Non-continuous clock: 0

Protocol Configuration Register: 0x201B
Generic Short packet Register: 0x0000
Line Count Virtual Channel 0: 0x0000

Interrupt Status Register: 0x0001


CSI-2 D-PHY Status:
-------------
D-PHY Control Register: 0x0002
Initialization Timer: 0xF4240
HS_TIMEOUT: 0x10005
ESC_TIMEOUT: 0x6400
Clock Lane Status: 0x0009
Data Lane0 Status: 0xCEB0048
Data Lane1 Status: 0xCEB0048
Data Lane2 Status: 0xCEB0048
Data Lane3 Status: 0xCEB0048

Data Lane0 Status: 0xCEB0048
Data Lane1 Status: 0xCEB0048
Data Lane2 Status: 0xCEB0048
Data Lane3 Status: 0xCEB0009

data lane is being in Low-Power mode for long time and very rarely transits to High-Speed mode.. this happens in PassThrough. differently, Color Pattern no such issues.

""Receiver reads multiple word counts esp. different for every packet."" - in pass it through mode

""Receiver reads multiple data type  esp. different for every packet."" - in pass it through mode


regards,
Prasanna Daram

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Adventurer
Adventurer
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Registered: ‎01-19-2018

@karnanlYes, Xilinx AXIS Stream FIFO primitive with 8192 buffer depth is used before the CSI-2 Tx IP.

this enabled the video timing for Tx IP for every resolution.

As soon as we have 8 lines of data buffered, we start the transfer to CSI-2 IP.
 
Regards,
Prasanna Daram

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @daram123

Please check this register value:
Interrupt Status Register: 0x0001

1. Pixel data under-run flag is asserted. You did not feed-data into MIPI CSI-2 TX SS fast-enough.    Once MIPI CSI-2 TX starts sending video data in HS-mode, you have to feed all video-data for one line.
    When MIPI CSI-2 TX is in HS-mode, and IP does not any data left in the buffer it will forced to stop HS-mode and go into LS-mode.

2. I am not sure what is your Pass-through design looks like.
    But I am expecting, you have a line-buffer to hold at least one line of video-data before
    asserting s_axis_tvalid to start HS-mode data transmission.

    XF_Daram_MIPI_Passthrough.png

Best regards
Leo

XF_Daram_MIPI_Passthrough.png
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Adventurer
Adventurer
718 Views
Registered: ‎01-19-2018

@karnanlYes, Xilinx AXIS Stream FIFO primitive with 8192 buffer depth is used before the CSI-2 Tx IP.

this enabled the video timing for Tx IP for every resolution.

As soon as we have 8 lines of data buffered, we start the transfer to CSI-2 IP.
 
Regards,
Prasanna Daram

View solution in original post

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