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Gloria_gao
Participant
Participant
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Registered: ‎11-15-2020

CSI2 RX IP constrain

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I am trying to use IMX219 in TE0726-03M , so I create a block design and put zynq ip and csi-2_rx ip, which can be seen as below:

1.png

However, I feel confused about the pin constrains for csi2 rx ip, the csi connector in TE0726-03M is as followed:

2.png

There are two pins of CSI_D0 and i consider that the csi_d0 with R48 and R48 should be connected to data lane 0 in LP mode. I don't know whether it is correct.

Besides, there are no pins for clk and data 1 in LP mode, what should I constrain the clk and data in LP mode.

I try to connect both the LP mode and HS mode to the same pins with different electronic standards, but the errors appear up.

3.png

5.png

7.png

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florentw
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Moderator
253 Views
Registered: ‎11-09-2015

HI @Gloria_gao 

I guess you can move forward with the progress from this topic right?

https://forums.xilinx.com/t5/Xilinx-IP-Catalog/cannot-find-csi-2-dphy-rx-ip-in-vivado2020-1-IP-catalog/m-p/1224628#M9838


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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florentw
Moderator
Moderator
254 Views
Registered: ‎11-09-2015

HI @Gloria_gao 

I guess you can move forward with the progress from this topic right?

https://forums.xilinx.com/t5/Xilinx-IP-Catalog/cannot-find-csi-2-dphy-rx-ip-in-vivado2020-1-IP-catalog/m-p/1224628#M9838


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Gloria_gao
Participant
Participant
252 Views
Registered: ‎11-15-2020

Yes, you're right.

Thank you again! ^_^

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