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Adventurer
Adventurer
1,625 Views
Registered: ‎08-16-2017

CSI2-RX Subsystem IO PIns

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Hi Folks,

In our design we have a camera sending CSI2 data over FMC. We use a ZU5EV in which we planned to use the LogiCORE CSI2-RX subsystem.

When configuring the IP core, it looks like the Clock IO pin which is on a GC IO pin (D4) is not allowed to be used. Is this a limitation of the IP core MIPI DPHY? 

How can we work around this? 

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @ziladdev,

Do you have any updates on this? Were the replies from @karnanl and @bpatil enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
Xilinx Employee
1,618 Views
Registered: ‎03-07-2018

Hi @ziladdev

Provide FPGA Device part no. and FPGA bank details (which you want interface with MIPI CSI-2 RX).

Provide Vivado version details.

How many MIPI CSI-2 instance and data lanes you intend to use?

Regards,

Bhushan

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Bhushan

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Adventurer
Adventurer
1,598 Views
Registered: ‎08-16-2017

FPGA: xczcu5ev-sfvc784-1-e

IO Bank : 66.

Vivado version: 2018.2

CSI-2 RX instances : #1 (now), will be extended to 4 cameras later. 

num-lanes: #4

io pinsio pins

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Xilinx Employee
Xilinx Employee
1,586 Views
Registered: ‎03-07-2018

Hi @ziladdev

The MIPI D-PHY IP core implements a D-PHY RX interface and provides PHY protocol layer support compatible with the MIPI CSI-2 RX interface (Check block diagram below). PG202 April 4, 2018 defines Pin and Bank Rules for MIPI DPHY in Appendix C.

MIPI CSI-2 RX DPHY.png

As per PG202, RX clock lane pins must be DBC, QBC and GC_QBC pins. 

D4 is not DBC, QBC and GC_QBC pin ( Check https://www.xilinx.com/support/packagefiles/zuppackages/xczu5evsfvc784pkg.txt for more details).

That's why you are not able to use D4 as clock IO pin for MIPI CSI-2 RX.

I will recommend to go through PG202 April 4, 2018: Appendix C to understand pin assignment of MIPI DPHY RX.

 

 

Regards,

Bhushan

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Bhushan

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Adventurer
Adventurer
1,564 Views
Registered: ‎08-16-2017

Patil,

I am aware of those, however the pins delivering clk and data lanes are fixed by hardware...

is there any potential work-around that doesn't involve redesigning the hardware to get the pins match....

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Xilinx Employee
Xilinx Employee
1,557 Views
Registered: ‎03-07-2018

Hi @ziladdev

As per my knowledge, there is no work-around for using non-clock pins for clock of MIPI CSI-2 RX.

Do you have access for only one bank pins for MIPI Camera's on FMC interface? or there is possibility of other HP bank pins can be available for MIPI CSI-2 RX Interface on FMC interface? 

Does all MIPI CSI-2 RX instances running at same speed? 

Regards,

Bhushan

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Regards,
Bhushan

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Adventurer
Adventurer
1,530 Views
Registered: ‎08-16-2017
GC is still a clock pin. I think the question really is, should we change the hardware as the pins seem to be fixed and do not match the ultrascale way of handling DPHY or is it a limitation of the IP core itself and we could perhaps find another IP core that can do the work.
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Xilinx Employee
Xilinx Employee
1,516 Views
Registered: ‎03-07-2018

@karnanl and @florentw Can you please comment on this issue?

Regards,
Bhushan

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Xilinx Employee
Xilinx Employee
1,491 Views
Registered: ‎03-30-2016

Hello @ziladdev

As mentioned by Bhushan  @bpatil  in previous post, MIPI CSI-2 RX/D-PHY shall use DBC/QBC pin for clock pin, you cannot use GC pin. This is device limitation. (Please see PG202 appendix C).

I think you will need to fix your board to use Xilinx MIPI IP.
There is 3rd party MIPI IP available (from NWL for example), but I believe this IP also using Xilinx MIPI D-PHY IP as a PHY IP so you will have the same restriction.

Thanks & regards
Leo

XF_20181121_MIPI_PIN.png
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Moderator
Moderator
1,405 Views
Registered: ‎11-09-2015

HI @ziladdev,

Do you have any updates on this? Were the replies from @karnanl and @bpatil enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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