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Registered: ‎03-20-2019

CSI2-TX line buffer with AXIS input

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Does the CSI2 TX Subsystem wait until a full line is in the line buffer before starting to send the line?

I am seeing buffer under-runs at 1080p60. I am using an AXIS input with 300 MHz clock, and 4 lane CSI output at 1 Gbps line rate. The video data is available at the input at regular intervals (i.e. 2 pixels every 16ns), but the CSI TX would have to wait for the whole line to be in the buffer.

Thanks,
Andy

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Andy andy.martin@videon-central.com 

>Does the CSI2 TX Subsystem wait until a full line is in the line buffer before starting to send the line?

The IP core will start processing and sending data after s_axis_tuser[0]=1 is received. (==Frame Start is asserted)

>I am seeing buffer under-runs at 1080p60. I am using an AXIS input with 300 MHz clock, and 4 lane CSI output at 1 Gbps line rate. The video data is available at the input at regular intervals (i.e. 2 pixels every 16ns), but the CSI TX would have to wait for the whole line to be in the buffer.


# Please take a look at PG260 Chapter3 "Clocking" section, to check if s_axis_aclk clock frequency is good. If you can share your XCI file, I can double check for you.
# When MIPI TX needs to send the data but there is no data left in the FIFO, buffer under-run will occur.
   Perhaps you need to implement a line-buffer to feed the data into MIPI TX core.


Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Andy andy.martin@videon-central.com 

>Does the CSI2 TX Subsystem wait until a full line is in the line buffer before starting to send the line?

The IP core will start processing and sending data after s_axis_tuser[0]=1 is received. (==Frame Start is asserted)

>I am seeing buffer under-runs at 1080p60. I am using an AXIS input with 300 MHz clock, and 4 lane CSI output at 1 Gbps line rate. The video data is available at the input at regular intervals (i.e. 2 pixels every 16ns), but the CSI TX would have to wait for the whole line to be in the buffer.


# Please take a look at PG260 Chapter3 "Clocking" section, to check if s_axis_aclk clock frequency is good. If you can share your XCI file, I can double check for you.
# When MIPI TX needs to send the data but there is no data left in the FIFO, buffer under-run will occur.
   Perhaps you need to implement a line-buffer to feed the data into MIPI TX core.


Thanks & regards
Leo

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Registered: ‎03-20-2019

Thank you. The s_axis_aclk is fast enough, but since the IP core starts sending immediately and the full line is not immediately available, it quickly under-runs. The line buffer in the IP core appears to only guard against over-runs. It would be nice if it could delay the start until there is a full line in the FIFO (s_axis_tlast is received).

I will implement an external line buffer.

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello andy.martin@videon-central.com 

>It would be nice if it could delay the start until there is a full line in the FIFO (s_axis_tlast is received).

It is not something that can be implemented soon,
But let me discuss this with our internal team.

Thanks for your feedback.

Regards
Leo

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