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Participant
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Registered: ‎01-26-2020

CameraLink receiver design. Some questions regarding delay and deserializer.

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Hello there

I an designing a CameraLink receiver to take a video stream from a camera and store it in memory for future use. the design consist of multiple stages:

- Convert the differential signal to single ended signal (using IBUFDS)

- PLL to generate required clocks

- Data delay and Deserializer (using IDELAYE2 and ISERDESE2)

- Memory storage

In the design I followed multiple documentations and posts here in the forums. I reached the Deserializer stage and test the implementation to find that the output of the Deserializer are not as describe in the CameraLink standard and the LVAL and FVAL signals are changing location every time I load the design to the FPGA. I thought about it for a while and come to conclusion that the problem is in the delay or deserializer primitive

My questions are:

- How to configure the IDELAYE2 and ISERDESE2 correctly for the CameraLink receiver? I attached my code down below

- I read once that the IDELAYE2 will not work properly if the input clock less than 59 MHz and my pixel clock is 48 MHz. Is it true? is there other primitive for slower clocks? Actually I am not sure why using pixel clock here rather than bit clock.

- The picture bellow is from the XAPP585 document. how to configure the ISERDESE2 to deal with this kind of clock shift? (as the clock rising edge is not align with the start of the signal stream as in the figure below)

asd.png

I am using:

- camera with 2 tap base CameraLink

- ZedBoard

- Vivado 2019.1

Sorry for the details but I wanted you to have full idea on what i am doing. I you could answer only one question or help with some ideas that would be great.

Thank you

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Teacher
Teacher
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Registered: ‎06-16-2013

Hi @ashura12 

 

>Any other ideas? can the rest share their thoughts?

 

Can you make sure clock signal ?

Or, can you share your this design ?

 

I guess it seems pll or recovery clock issue.

So, would you make sure it ?

 

Best regards,

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Contributor
Contributor
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Registered: ‎05-25-2018

Hi,

  Have you tried this XAPP

https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf

Can help you more if you need a packaged IP

  

In Service,
Kamalesh Vikramasimhan
www.yantravision.com
Participant
Participant
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Registered: ‎01-26-2020

Hi @kvikramaxlnx 

Thank for the help

Yes, I went through the document. The clock pic is from the XAPP585 and it says in one of the section that the design will not work with clock speed slower than 59 MHZ which is one of my questions that need an answer. I have tried the source design but it does not work, the same output.

 

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Contributor
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Registered: ‎05-25-2018

@ashura12 only per bit deskew gets disabled. 

In Service,
Kamalesh Vikramasimhan
www.yantravision.com
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Participant
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Registered: ‎01-26-2020

@kvikramaxlnx 

I am sorry, I don't understand what you mean.

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Contributor
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Registered: ‎05-25-2018

@ashura12 your tap delay setting might not work with granularity expected. 

At lower frequencies you might not need that tap delay setting (to deskew data). Your design itself should work

In Service,
Kamalesh Vikramasimhan
www.yantravision.com
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Participant
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Registered: ‎01-26-2020

@kvikramaxlnx 

That is what I thought but the results was not as expected. I did everything as described in the CL specification and xilinx documents but It seems I am missing something.

Any other thoughts?

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Contributor
Contributor
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Registered: ‎05-25-2018

@ashura12 can you post the results ?

In Service,
Kamalesh Vikramasimhan
www.yantravision.com
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Registered: ‎01-26-2020

@kvikramaxlnx 

I am using the ZedBoard LEDs to see the output I can post a photos but there is no point for you so I will describe the problem.

According to the CL spec sheet, the LVAL, FVAL, and DVAL signals will be in the fourth data line in the 24, 25, 26 bit out of the 28-bit the base link transmit. After I finished my design I test it using external monitor but the monitor didn't receive any signal (I test it using pattern generator and it works fine) so I decided to trace my step backward and I found that the timing signals above are not in the right location and in the third data line. in addition, they change bit location every time I reload the bitstream to the ZedBoard. I used the LEDs to display all 28 bit coming from the deserializer to see if I am receiving something or not and to see if the timing signals there or not.

This is the problem. I search the internet and come to conclusion that the delay or the deserializer is causing the problem due to the reasons I mentioned above.

Any thoughts?

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Contributor
Contributor
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Registered: ‎05-25-2018

Hi @ashura12 

  You maybe better off using ILA to observe the incoming signals from CameraLink (Display can be used once you have lock on the framing signals).

It's possible that there is bitslip and the location of FVAL and LVAL have gone off.

If you can look at ILA and estimate it, you can have a bitslip logic to get it fixed.

 

In Service,
Kamalesh Vikramasimhan
www.yantravision.com
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Participant
Participant
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Registered: ‎01-26-2020

Hi @kvikramaxlnx 

I spent the last two days trying to use the ILA but I couldn't manage to extract useful results because it always giving me warning about the clock signal deriving the ILA and when I solve it the waveform window shows "no content" or it give an error (after triggering the ILA) saying the data is corrupted.

Any other ideas? can the rest share their thoughts?  

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Teacher
Teacher
349 Views
Registered: ‎06-16-2013

Hi @ashura12 

 

>Any other ideas? can the rest share their thoughts?

 

Can you make sure clock signal ?

Or, can you share your this design ?

 

I guess it seems pll or recovery clock issue.

So, would you make sure it ?

 

Best regards,

View solution in original post

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Participant
Participant
199 Views
Registered: ‎01-26-2020

Hi @watari 

 

Finally I managed to make it work.

It turns out that the PLL was not working correctly when I connect it to the Camera clock signal and I had to redesign the receiver to accept the clocking wizard IP. I wasted too much time fixing ILA IP problems and some times the solution is to re design the project from the beginning, it was so annoying.

 

Thank you so much @watari and @kvikramaxlnx for your help. I really appreciate it.

 

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