Can I drive AXI4-Stream to Video without configuration in PS?

[joelschad]

I am using Vivado 2019.1 and am porting a video system from a Zynq 7 SoC to a Zynq US+.

Because the firmware/PS side of the design is not yet ready and my expertise on PS programming and configuration is almost nil, I am simply trying to produce a test pattern on the US+ design with effectively no access to the PS.

On the original Zynq 7 design, which did have PS firmware ultimately driving the screen content, a Xilinx AXI Video Direct Memory Access (VDMA) block and a video timing generator block (Avnet's ALI3 Static Video Timing Generator) drove an AXI4-Stream to Video block. This block was successfully producing pixel and timing data.

Now with the US+, however, my AXI4-Stream to Video block is outputting nothing; underflow is high, locked never goes high, and my data and sync/blank ports are always low.

I have tried hooking up the Xilinx Test Pattern Generator (TPG) and the Video Timing Controller (VTC). The VTC is delivering timing data, but the AXI4-Stream to Video block stays dormant. It is unclear what, if any, configuration of these blocks need to be done on the PS side.

My question is: How can I get the AXI4-Stream to Video block to produce outputs with NO configuration from the PS side?

No data is coming out of AXI4-Stream to Video. The screenshot below was taken before the TPG was added, when the VDMA was feeding the AXI4-Stream to Video, so the video pixel data was all zeroes, but the vid_hsync and vid_vsync were always low in either case.

[florentw]

Hi @joelschad 

The

AXI4-Stream to Video out itself does not require any configuration from the processor. However the Test Pattern Generator needs to be configured and started from the processor. This is why yo are not getting any data.

If you are starting with Video design, you might want to read my Video Series. The Video Series 21: TPG Application on ZC702 is talking about the TPG programing. This is based on Zynq-7000 but the same principle appleis for Zynq US+

Regards

[joelschad]

Thanks. Very informative!

Quick question:

In your tutorial example, YUV422 corresponds to Data = 0x2:

// Set Color Space to YUV422
XV_tpg_Set_colorFormat(&tpg_inst, 0x2);

However, I don't see anything in the API guide or the header files about what value I should use for RGB or RGBA.

For function XV_tpg_Set_colorFormat(XV_tpg *InstancePtr, u32 Data), where can I find a list of which Data values correspond to which color format?

[joelschad]

Oops. It was in the Product guide for the Test Pattern Generator:

• 0x0 - RGB video format
• 0x1 - YUV 444 video format
• 0x2 - YUV 422 video format
• 0x3 - YUV 420 video format

[florentw]

Hi @joelschad 

Yes I documented this in a previous video series:

https://forums.xilinx.com/t5/Video/Video-Beginner-Series-4-Simulation-with-the-Xilinx-TPG-IP/td-p/855134

I want to avoid repeating too much, else each one would be too long ;)

[florentw]

HI @joelschad 

Were you able to make you project working?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,

[joelschad · Accepted solution]

Basically yes.I was not able to get the AXI4-Stream to Video block to output data without some configuration from the PS side. I did not use the Test Pattern Generator block.

That said, a FW engineer was able to help me get the PS side code together to drive the IP, and I was able to get video to appear on the screen.

[aoifem]

Hi  @joelschad 

Is your issue now resolved? 

If so, please kindly mark the response which helped as a solution (click on "Accept as solution" button below the reply).
 
If your issue was not solved/answered in this thread, would you mind sharing more details about your solution for the community?
 
Thanks and Regards,