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abstract
Observer
Observer
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Registered: ‎06-12-2017

Cannot change VCU CORE Clk

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I'd like to change the encoder clock of VCU (of ZynqMP). When I enter 333 as CORE Clk, then press OK, the console of Vivado shows the following error.

 

ERROR: [BD 41-245] set_property error - Validation failed for parameter 'Max Number of Encoder Streams(NO_OF_STREAMS) with value '0' for BD Cell 'vcu_0'. This configuration exceeds the VCU capabilities !
Customization errors found on 'vcu_0'. Restoring to previous valid configuration.
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

 

As a reference, I attach the image of the settings of another tab ('Basic Configuration').

I can change other settings (eg. Memory Resource Type) and then pressing "OK" doesn't complain. Also, when I select VCU, then change Block Properties > Properties tab > CONFIG > NO_OF_STREAMS to 1, the same error occurs where the value '0' is now '1'.

The version is 2019.1. Am I missing something obvious?

-------------

P.S.

I noticed increasing the clock frequency does not cause the problem. So the value 667 is the minimum value? The resolution of the image to the encoder is much lower than the displayed settings (nearly 4K and more). But I suspect just lowering the resolution in the dialog might cause problems in vcu driver on the Linux side (regarding memory allocation), I'd like to keep the resolution settings as is, just lowering the frequency (because the frame rate is below 10fps). Isn't that possible?

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Update

Because the above method doesn't work now, I forced the PLL divisor to another value after PetaLinux boots.

# devmem 0xA0140030
0x0001021
# devmem 0xA0140030 32 0x00001041
# devmem 0xA0140030
0x0001041

Set ENC_CORE_CTRL (VCU_SLCR) register, DIVISOR0 value from 2 to 4. It seems the framerate is OK. But I still want to know the valid way to modify the clock.

vcu.png
vcu2.png
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Accepted Solutions
florentw
Moderator
Moderator
192 Views
Registered: ‎11-09-2015

HI @abstract 

The encoder core clock is related to the resolution. If you decrease too much the clock then you might not be able to meet the requirements for the input stream.

I can decrease the core clock to 333 MHz if I reduce the size of the encoder stream to 1280x720 (1 stream) or if I change the input to 4K@15Hz .

So you need to make sure both configurations are coherent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

3 Replies
florentw
Moderator
Moderator
193 Views
Registered: ‎11-09-2015

HI @abstract 

The encoder core clock is related to the resolution. If you decrease too much the clock then you might not be able to meet the requirements for the input stream.

I can decrease the core clock to 333 MHz if I reduce the size of the encoder stream to 1280x720 (1 stream) or if I change the input to 4K@15Hz .

So you need to make sure both configurations are coherent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

florentw
Moderator
Moderator
168 Views
Registered: ‎11-09-2015

HI @abstract 

Any update on this topic? Is the answer provided enough for you?

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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abstract
Observer
Observer
155 Views
Registered: ‎06-12-2017

Hi @florentw ,

Thank you for answering. The encoder frequency I set by devmem command looks fine for my resolution/framerate, so I have stopped to seek the way to change the frequncy from Vivado GUI.

Regards,

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