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phil.d.dawson
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Registered: ‎09-14-2018

Changing HDMI TX Colour Depth (How to switch from 10bit to 8bit?)

Hi,

I'm working with the VCU TRD 2018.3 on a ZCU106 board.

I have modified the Block Design so the HDMI RX and HDMI TX Subsystems support upto 10bit Mamimum colour depth. This builds and correctly outputs 10bit over HDMI:

root@zcu106_vcu_trd:/sys/devices/platform/amba_pl@0# cat a0020000.v_hdmi_tx_ss/hdmi_info

  Stream Info
 -------------
        Color Format:     RGB
        Color Depth:      10
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       1920x1080@60Hz
        Pixel Clock:      148500000

  Stream Timing
 ----------------

        HSYNC Timing: hav=1920, hfp=88, hsw=44(hsp=1), hbp=148, htot=2200
        VSYNC Timing: vav=1080, vfp=04, vsw=05(vsp=1), vbp=036, vtot=1125


Tx Info
--------
TX Mode - HDMI
HDMI Video Mask is Disabled

Scrambled: 0
Sample rate: 1
Audio channels: 0

root@zcu106_vcu_trd:/sys/devices/platform/amba_pl@0# cat a0020000.v_hdmi_tx_ss/vphy_info
TX: QPLL0
RX: CPLL
TX state: idle
RX state: idle

QPLL0 settings
-------------
M : 1 - N : 80 - D : 8

CPLL settings
-------------
M : 1 - N1 : 5 - N2 : 4 - D : 4

RX MMCM settings
-------------
Mult : 10 - Div : 1 - Clk0Div : 20 - Clk1Div : 10 - Clk2Div : 20

TX MMCM settings
-------------
Mult : 8 - Div : 1 - Clk0Div : 16 - Clk1Div : 8 - Clk2Div : 20

DRU Settings
-------------
Version  : 7
DRU is disabled

Tx Ref Clk: 185626624 Hz

However I can't figure out how to change the color depth of the output. I would like to be able to switch between 8bit and 10bit color depths from the command line or software.

It also seems to not be honouring the EDID of the connected sink which does not have the 30bits/pixel (10bits/colour) option set in the HDMI Vendor Specific Data Block.

My main question is this: How can I change the colour depth of the output at run time?

Thanks,

Phil

 

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watari
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Registered: ‎06-16-2013

Hi @phil.d.dawson 

 

It's hard to explain it without your modified design.

 

But, the best way is to modify EDID on sink device which you already mentioned.

 

[Notice]

Take care Tx ref clock between 8bit mode and 10bit mode.

 

Best regards,

florentw
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Registered: ‎11-09-2015

Hi @phil.d.dawson 

Do you have any udpate on this? Did you follow @watari advice and edited the EDID?

Note that this is up to the user to take care of the EDID, this is not supported by Xilinx


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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phil.d.dawson
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Registered: ‎09-14-2018

Hi, Apologies for the lack of updates. The connected sink did not have 10bit support enabled in the EDID, however the HDMI TX subsystem was outputting 10bit data anyway (after making the required modifications to the TX ref clock). Even if the connected sink did advertise 10bit support in its EDID we would still like to be able to programmatically force the output to 8bits in some cases (depending on sink capabilities, and incoming/outgoing video formats). Is there no way to force the drivers to use 8 or 10bit mode? Thanks, Phil
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florentw
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Registered: ‎11-09-2015

Hi @phil.d.dawson 

Can you try the VCU TRD 2019.2 and see if the issue is still present (ie. the HDMI does not read the EDID).

Then the gstreamer pipeline should control  between 10bit and 8 bits if supported by the design


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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phil.d.dawson
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Registered: ‎09-14-2018

Hi @florentw

I've also tried VCU TRD 2019.2 (10G). I made the following modifications to the block design to enable 10 bit input and output:

set_property -dict [list CONFIG.C_MAX_DATA_WIDTH {10}] [get_bd_cells hdmi_input/v_proc_ss_0]
set_property -dict [list CONFIG.MAX_DATA_WIDTH {10} CONFIG.HAS_RGBX10 {1} CONFIG.HAS_YUVX10 {1} CONFIG.HAS_Y_UV10 {1} CONFIG.HAS_Y_UV10_420 {1} CONFIG.HAS_Y10 {1}] [get_bd_cells hdmi_input/v_frmbuf_wr_0]
set_property -dict [list CONFIG.MAX_DATA_WIDTH {10} CONFIG.HAS_RGBX10 {1} CONFIG.HAS_YUVX10 {1} CONFIG.HAS_Y_UV10 {1} CONFIG.HAS_Y_UV10_420 {1} CONFIG.HAS_Y10 {1}] [get_bd_cells hdmi_input/v_frmbuf_wr_1]
set_property -dict [list CONFIG.MAX_DATA_WIDTH {10} CONFIG.HAS_RGBX10 {1} CONFIG.HAS_YUVX10 {1} CONFIG.HAS_Y_UV10 {1} CONFIG.HAS_Y_UV10_420 {1} CONFIG.HAS_Y10 {1}] [get_bd_cells hdmi_input/v_frmbuf_wr_2]
set_property -dict [list CONFIG.C_MAX_BITS_PER_COMPONENT {10}] [get_bd_cells hdmi_input/v_hdmi_rx_ss_0]
set_property -dict [list CONFIG.MAX_DATA_WIDTH {10}] [get_bd_cells hdmi_output/v_mix_0]
set_property -dict [list CONFIG.MAX_DATA_WIDTH {10} CONFIG.HAS_RGBX10 {1} CONFIG.HAS_YUVX10 {1} CONFIG.HAS_Y_UV10 {1} CONFIG.HAS_Y_UV10_420 {1} CONFIG.HAS_Y10 {1}] [get_bd_cells hdmi_output/v_frmbuf_rd_0]
set_property -dict [list CONFIG.C_MAX_BITS_PER_COMPONENT {10}] [get_bd_cells hdmi_output/v_hdmi_tx_ss_0]

(following the steps in https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/176914576/Zynq+UltraScale+MPSoC+VCU+TRD+2019.2+-+Run+and+Build+Flow to rebuild the PL and the Petalinux Image using the new hw description).

If i cat /sys/bus/platform/devices/a0000000.v_hdmi_rx_ss/hdmi_info I can see that 8 and 10 bit inputs are detected correctly. However cating .../v_hdmi_rx_ss/hdmi_info shows the output mode to always be 4k60 8bit, even when connected to a device with a 10bit EDID.

I can use modetest to change the output resolution to 1080p60 (to leave headroom to choose betwen 8 and 10 bit modes without breaching the 600MHz TMDS clock limit of HDMI2). This does change the mode but also gives a trace from the kernel:

root@zcu106_vcu_trd:/sys/bus/platform/devices# modetest -D a0070000.v_mix -s 40:1920x1080-60@BG24 -w 36:"alpha":0
setting mode 1920x1080-60Hz@BG24 on connectors 40, crtc 38
[  181.662457] ------------[ cut here ]------------
[  181.667071] driver forgot to call drm_crtc_vblank_off()
[  181.672329] WARNING: CPU: 2 PID: 2885 at drivers/gpu/drm/drm_atomic_helper.c:1000 drm_atomic_helper_commit_modeset_disables+0x3b0/0x3b8
[  181.684484] Modules linked in: dmaproxy(O) al5d(O) al5e(O) allegro(O) xlnx_vcu xlnx_vcu_clk xilinx_hdmi_tx(O) xilinx_hdmi_rx(O) xlnx_vcu_core dp159(O) xilinx_vphy(O) mali(O) uio_pdrv_genirq
[  181.701355] CPU: 2 PID: 2885 Comm: modetest Tainted: G           O      4.19.0-xilinx-v2019.2 #1
[  181.710127] Hardware name: ZynqMP ZCU106 RevA (DT)
[  181.714904] pstate: 60000005 (nZCv daif -PAN -UAO)
[  181.719679] pc : drm_atomic_helper_commit_modeset_disables+0x3b0/0x3b8
[  181.726189] lr : drm_atomic_helper_commit_modeset_disables+0x3b0/0x3b8
[  181.732698] sp : ffffff801718ba00
[  181.735996] x29: ffffff801718ba00 x28: ffffffc85f080800
[  181.741300] x27: ffffffc87bb6d800 x26: 0000000000000000
[  181.746604] x25: 0000000000000038 x24: ffffff80091c725b
[  181.751908] x23: ffffff8008d74ed8 x22: 0000000000000000
[  181.757212] x21: ffffffc85e26f000 x20: ffffffc86015d090
[  181.762516] x19: ffffffc87b96ea80 x18: 0000000000000010
[  181.767820] x17: 0000000000000000 x16: 0000000000000000
[  181.773116] x15: ffffffffffffffff x14: ffffff8009148648
[  181.778420] x13: ffffff80891e7f0f x12: ffffff80091e7f17
[  181.783724] x11: ffffff800915a000 x10: ffffff801718b6e0
[  181.789027] x9 : 00000000ffffffd0 x8 : ffffff8008543da8
[  181.794332] x7 : 7264206c6c616320 x6 : 00000000000001d4
[  181.799635] x5 : 0000000000000003 x4 : 0000000000000000
[  181.804931] x3 : 0000000000000000 x2 : ffffffffffffffff
[  181.810226] x1 : 786b713a49afa000 x0 : 0000000000000000
[  181.815521] Call trace:
[  181.817955]  drm_atomic_helper_commit_modeset_disables+0x3b0/0x3b8
[  181.824118]  drm_atomic_helper_commit_tail+0x20/0x78
[  181.829065]  commit_tail+0x74/0x78
[  181.832451]  drm_atomic_helper_commit+0xc8/0x140
[  181.837053]  drm_atomic_commit+0x48/0x58
[  181.840967]  drm_atomic_helper_set_config+0xa0/0xb0
[  181.845830]  drm_mode_setcrtc+0x144/0x5d8
[  181.849830]  drm_ioctl_kernel+0xb4/0x100
[  181.853736]  drm_ioctl+0x204/0x3a8
[  181.857125]  do_vfs_ioctl+0xb8/0x8a0
[  181.860690]  ksys_ioctl+0x44/0x90
[  181.863989]  __arm64_sys_ioctl+0x1c/0x28
[  181.867897]  el0_svc_common+0x84/0xd8
[  181.871550]  el0_svc_handler+0x68/0x80
[  181.875283]  el0_svc+0x8/0xc
[  181.878146] ---[ end trace 37774d24b7f172c1 ]---

The planes listed in modetest -D a0070000.v_mix have formats of NV12/AR24/BG24 so it doesn't seem like I could choose between 8 or 10 bit output using modetest (unless I'm missing something).

If i run root@zcu106_vcu_trd:/media/card/config# vcu_gst_app input-1080p.cfg when I have an 8 bit input it works fine. If i Have a 10 bit input I get an error:

root@zcu106_vcu_trd:/media/card/config# vcu_gst_app input-1080p.cfg
/*************************Pipeline Information Start*************************/
Pipeline Info : On
Fps Info : On
APM Info : On
Output goes on : HDMI
Frame rate : 60
Number of Source is : 1
Use case is to : Display
Device Type : HDMI
Format : NV12
Width : 1920
Height : 1080
Raw : True
Accelerator flag : False
Enable_scd flag : False
Enable_roi flag : False
Enable_llp2 flag : False
Src Type : Live Src
URI : file:///media/usb/test_1.ts
/*************************Pipeline Information End*************************/
ERROR(../vcu_gst_apps/lib/vcu_video_lib/src/vcap_hdmi.c:211) : Unable to setup formats: Invalid argument (22)
Aborted

where input-1080p.cfg is the same as the default input.cfg in /media/card/config but with just the input resolution changed:

root@zcu106_vcu_trd:/media/card/config# cat input-1080p.cfg
Common Configuration    : START
Num Of Input            : 1
Output                  : HDMI
Out Type                : Display
Frame Rate              : 60
Exit


Input Configuration     : START
Input Num               : 1
Input Type              : hdmi
Uri                     : file:///media/usb/test_1.ts
Raw                     : TRUE
Width                   : 1920
Height                  : 1080
Exit

...

It still feels like I'm missing a simple command to set the colour depth of the hdmi_tx_ss but I can't see any thing appropriate in the vcu_gst_app config or the modetest commands.

Thanks,

Phil

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kvasantr
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Registered: ‎04-12-2017

Hello @phil.d.dawson 

Can you try running following modetest:

modetest -M xlnx -s 31@29:1920x1080-60@XB30 &

You will need to change the connector ID as per your design to make HDMI TX to work for 10bit.

regards

Kunal

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