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Visitor
Visitor
7,418 Views
Registered: ‎09-18-2007

Connecting external differential clock to System Generator black box block

I have a design that is clocked by an external differential clock. In SysGen, I use the black box configuration wizard to point to the source vhdl file.

How should I connect the external differential clock in Simulink?

 

Regards,

SY 

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Xilinx Employee
Xilinx Employee
7,417 Views
Registered: ‎08-02-2007

Since you can't explicitly have clocks wired up in Simulink you need to select one of the clocking options available in the Sysgen Token. Details on these are specified in the sysgen users guide.
Message Edited by rjduran on 06-16-2008 03:04 PM
RJ Duran
Customer Application Engineer
Technical Support: http://www.xilinx.com/support
Xilinx User Community: http://forums.xilinx.com
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Visitor
Visitor
7,414 Views
Registered: ‎09-18-2007

Hi RJ,

 

I'm targeting this for hardware co-simulation. So the clock pin location is fixed. I'm using an external differential clock that isn't on the ML506 board.

 

Also, there's only one space to put the pin location in the SysGen token. How do I specify differential clock pins?

 

Thanks,

SY 

Message Edited by syuan523 on 06-16-2008 02:10 PM
Message Edited by syuan523 on 06-16-2008 02:11 PM
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Newbie
Newbie
4,351 Views
Registered: ‎07-01-2009

Do you find an issue to your problem ?

If it's the case I would know what this is 

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