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Observer
Observer
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Registered: ‎03-23-2017

D-PHY reference clock

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Xilinx D-PHY requires a 200 MHz reference clock, and there is a note that this should be from an external oscillator.  But it also says you may use one PLL or MMCM, but not cascaded ones.  Is it acceptable to use the PS PLL in Zynq Ultrascale+ fed by a 33.33 MHz crystal oscillator to generate this clock?

"IMPORTANT! core_clk should be either coming from the on-board oscillator or the single MMCM or the PLL from target FPGA device. core_clk should not be generated from the cascaded MMCM blocks"

Based on the somewhat mangled words, I think this should be OK.  Also, it seems to work when I try it, but there is no jitter analysis to back this up.  What do you think?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: D-PHY reference clock

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Hello @jhallen 

Clock from PS PLL should be good to feed D-PHY IP 200MHz clock.
( As long as timing is met )

Hope this helps.

Thanks
Leo

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Xilinx Employee
Xilinx Employee
293 Views
Registered: ‎03-30-2016

Re: D-PHY reference clock

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Hello @jhallen 

Clock from PS PLL should be good to feed D-PHY IP 200MHz clock.
( As long as timing is met )

Hope this helps.

Thanks
Leo

View solution in original post