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Registered: ‎05-29-2019

DDC issue on HDMI 1.4/2.0 Receiver IP

Hello,

In our board we're using 4 Zynqs, with two HDMI 1.4/2.0 Receiver IP per Zynq.
Totally 8 HDMI Rx inputs per board.
We have an issue on DDC of input 8 of the board.
Therefore EDID and also HDCP tests fail on this input.

After some investigation we discovered that SCL/SDA rising time on this input a slightly higher then on the other ones.
No oveshoot/undershoot are observed at all.
However it's still within the spec of I2C (attached scope shot).

We have register packed in IOB on these signals.
Attached Vivado definitions on these pins (HP bank).

I did not find any parameters to be set regarding IIC controller in hdmi_rx_ss IP.
This is neither in Xilinix HDMI Rx software drivers code or block_design or documentation.
Hdmi_rx_ss IP apparently using 100MHz clock we provided in the block design.
Can you confirm that default parameters of DDC/IIC are for 100MHz ?

Do you have any clue and suggesthions for the wotkaround.

Best regards.
Boris Barak.

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Teacher
Teacher
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Registered: ‎06-16-2013

Hi boris.barak@vitec.com 

 

Would you share your observed wave form ?

I can't find any picture in your post...

 

Best regards,

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Registered: ‎05-29-2019

Hi,

Sorry' I've obviously forgot to attach.

Attached DDC pins properties in Vivado and DDC lines signals, measured next to Zynq.

Boris Barak.

DDC_pads_Vivado.png
scope_DDC_SCL=CH1.jpeg
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Explorer
Explorer
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Registered: ‎06-13-2012

Hi boris.barak@vitec.com 

 

I'm facing the same or similar problem, I see the SCL and SDA signals with a ila scope that the source is trying to read the edid but the tristate signal never changes, so a not acknowledge is generated.
Did you solve the issue?
Regards

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Registered: ‎05-29-2019

Try to reduce SCL/SDA signals rise time first.

Do do this the pull-up resistors on the board can be reduced to about 1 kOhm.

In addition see what the frequency of the clock, sampling these signals within Xilinix IP. 

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Explorer
Explorer
204 Views
Registered: ‎06-13-2012

Hi boris.barak@vitec.com 

Thank you for your answer, actually the rise and falling time is perfect, no big delays like in your scope but the IP is not answering, the pin I used are configured like the picture of your previous post.
Connecting a video generator, the video input is detected and I can read the video details as resolution etc. but the generator can't read the edid of the receiver.

Than you for your support

Regards

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Explorer
Explorer
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Registered: ‎06-13-2012

Hi boris.barak@vitec.com ,
The only way to make it work is to change the pins of the FPGA, using two pins in a 3.3V powered bank the receiver IP works ok. I don't understand why using two pins in a 1.8V high performance bank with a i2c translator I see good signals with the oscilloscope and internal ILA but the IP is not working.
Regards

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Registered: ‎05-29-2019

I suggest to open a service request to Xilinix support.

This way the FAE will follow your specific case, trying to make a resolution.

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