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tiger193

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07-07-2011 05:50 AM - edited 07-07-2011 05:51 AM

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Registered:
07-04-2011

I have a question about the formula which is used to calculate the phase increment for a desired output frequency.

The Xilinx datasheet for the DDS Compiler v4.0 specifies different formulas.

http://www.xilinx.com/support/documentation/ip_documentation/dds_ds558.pdf

On page 3 a formula written on the left hand side below Figure 1 states:

f_out = phase_increment_value * f_clk / 2^B_capital_ Theta

=> formula (1)

where 2^B_capital_ Theta is the Lookup Table Depth

On the other hand on page 4 is written:

f_out = phase_increment_value * f_clk / 2^B_lowercase_Theta

=> formula (2)

where B_lowercase_Theta is the Phase width.

From a logical standpoint I would guess that formula 1 is correct.

After some experimenting with SystemGenerator It seems as if formula (2) would be correct.

Any comments about this?

Attachments: figure 1 from Xilinx DDS v4.0 Datasheet

1 Solution

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eschei

Xilinx Employee

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07-07-2011 07:47 PM

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Registered:
02-09-2009

Yes, you can use either formula, both are correct. However, if you use the upper case theta, refering to the post quantized B, the you will need to use a decimal at the corresponding position for your phase increment value. Since multiplying by a power of 2 corresponds to shifting the decimal position this will work out correctly.

example: say you want an fout of 5 MHz using a 100 MHz clock. Assume that you have a 31 bit accumulator and 14 bit look-up table address. You can calculate the phase increment value two ways:

5000000*(2^31)/100000000 = 1.073741824000000e+008

or

5000000*(2^14)/100000000 = 8.192000000000001e+002

This is actually the same if we consider for the second equation a binary point at position 17 (31-14=17):

1.073741824000000e+008 * 2^-17 = 8.192000000000001e+002

Regards,

-es

5 Replies

austin

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07-07-2011 08:38 AM

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02-27-2008

The phase increment is the width of the accumulator. If the accumulator is 16 bits, then the resolution (smallest frequency step) is 1/65536 of the clock frequency.

Perhaps the confusion here is 'width' and 'depth' of the lookup table. The address to the lookup table is the number of bits in the accumulator. Is that width, or depth? I would say depth, as that is the number of words in the table. The lookup table resolution could be the same as the address value (say 16 bits, and each addressed value returns 16 bits). The width of the lookup table provides the sine and cosine value to some resolution.

So, width of accumulator, depth of lookup table makes sense to me. Both formulas are correct.

Austin Lesea

Principal Engineer

Xilinx San Jose

Principal Engineer

Xilinx San Jose

eschei

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07-07-2011 07:47 PM

6,012 Views

Registered:
02-09-2009

Yes, you can use either formula, both are correct. However, if you use the upper case theta, refering to the post quantized B, the you will need to use a decimal at the corresponding position for your phase increment value. Since multiplying by a power of 2 corresponds to shifting the decimal position this will work out correctly.

example: say you want an fout of 5 MHz using a 100 MHz clock. Assume that you have a 31 bit accumulator and 14 bit look-up table address. You can calculate the phase increment value two ways:

5000000*(2^31)/100000000 = 1.073741824000000e+008

or

5000000*(2^14)/100000000 = 8.192000000000001e+002

This is actually the same if we consider for the second equation a binary point at position 17 (31-14=17):

1.073741824000000e+008 * 2^-17 = 8.192000000000001e+002

Regards,

-es

tiger193

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07-08-2011 01:56 AM

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Registered:
07-04-2011

Thanks a lot for your helpful replies. I gave both of you kudos :smileyhappy:

ywu

Xilinx Employee

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07-13-2011 01:59 PM

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Registered:
11-28-2007

Strictly speaking the formula (1) wtih the capital Theta is incorrect because using the width of the quantizer output will not provide the same frequency resolution. I will file a change request to get it fixed.

@tiger193 wrote:

I have a question about the formula which is used to calculate the phase increment for a desired output frequency.

The Xilinx datasheet for the DDS Compiler v4.0 specifies different formulas.

http://www.xilinx.com/support/documentation/ip_documentation/dds_ds558.pdf

On page 3 a formula written on the left hand side below Figure 1 states:

f_out = phase_increment_value * f_clk / 2^B_capital_ Theta

=> formula (1)

where 2^B_capital_ Theta is the Lookup Table Depth

On the other hand on page 4 is written:

f_out = phase_increment_value * f_clk / 2^B_lowercase_Theta

=> formula (2)

where B_lowercase_Theta is the Phase width.

From a logical standpoint I would guess that formula 1 is correct.

After some experimenting with SystemGenerator It seems as if formula (2) would be correct.

Any comments about this?

Attachments: figure 1 from Xilinx DDS v4.0 Datasheet

Cheers,

Jim

Jim

tiger193

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07-22-2011 04:04 AM

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Registered:
07-04-2011

Hi Jim,

Cool that you initiated a action that will correct the documentation error.

Little Mistakes in the documentation can always happen, but as a customer it is good to know that even such small failures are corrected over time. :smileyhappy: