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TonyWu_Wonder
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Registered: ‎10-05-2020

DP1.2 TX implementaion faild in xc7z035fbg676-2

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I implement Dp_tx project like the IP example from ZCU102.
And GTX pin assign like :

TonyWu_Wonder_0-1605849836589.pngTonyWu_Wonder_1-1605849846928.png

TonyWu_Wonder_2-1605850465849.png


1. Errors are reported in Place design:


[Place 30-801] Sub-optimal placement for an IBUFDS / GT component pair (Same clock region non-intelligent pin mode). If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets dp_ss_i/vid_phy_controller_0/inst/gt_usrclk_source/Q0_CLK1_GTREFCLK_OUT] >

dp_ss_i/vid_phy_controller_0/inst/gt_usrclk_source/gen_standard_clocking.ibufds_instQ0_CLK1 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y6
dp_ss_i/vid_phy_controller_0/inst/gt_common_inst/gtxe2_common_i (GTXE2_COMMON.GTREFCLK1) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y2
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt0_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK1) is locked to GTXE2_CHANNEL_X0Y8
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt1_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK1) is locked to GTXE2_CHANNEL_X0Y9
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt2_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK1) is locked to GTXE2_CHANNEL_X0Y10
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt3_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK1) is locked to GTXE2_CHANNEL_X0Y11

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_gtxcommon_gtxchannel
Status: PASS
Rule Description: A GTXCommon driving a GTXChannel must both be in the same clock region
dp_ss_i/vid_phy_controller_0/inst/gt_common_inst/gtxe2_common_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y2
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt0_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y8
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt1_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y9
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt2_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y10
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt3_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y11

Clock Rule: rule_bufds_gtx
Status: PASS
Rule Description: An IBUFDS driving a GTX in non-intelligent pin mode.
dp_ss_i/vid_phy_controller_0/inst/gt_usrclk_source/gen_standard_clocking.ibufds_instQ0_CLK0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y4
dp_ss_i/vid_phy_controller_0/inst/gt_common_inst/gtxe2_common_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y2
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt0_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y8
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt1_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y9
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt2_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y10
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt3_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y11

Clock Rule: rule_gt_bufg
Status: PASS
Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt0_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i (GTXE2_CHANNEL.RXOUTCLK) is locked to GTXE2_CHANNEL_X0Y8
and dp_ss_i/vid_phy_controller_0/inst/gt_usrclk_source/rxoutclk_bufg1_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

2. After first step, if I add <set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets dp_ss_i/vid_phy_controller_0/inst/gt_usrclk_source/Q0_CLK1_GTREFCLK_OUT]>
into constraint, errors are reported in Route design:

[DRC PDCN-2713] GTXE2_COMMON_valid_IBUFDS_GT_connection: GTXE2_COMMON dp_ss_i/vid_phy_controller_0/inst/gt_common_inst/gtxe2_common_i uses multiple REFCLK pins which prevents pin swapping and is driven by an IBUFDS_GTE2 dp_ss_i/vid_phy_controller_0/inst/gt_usrclk_source/gen_standard_clocking.ibufds_instQ0_CLK1 which as placed does not connect to the chosen REFCLK pin dp_ss_i/vid_phy_controller_0/inst/gt_common_inst/gtxe2_common_i/GTREFCLK1. Either use a single REFCLK so pin swapping can select a valid pin, or change the IBUFDS_GTE2 placement, or use a REFCLK pin (GTREFCLK0) which matchs the IBUFDS_GTE2 placement.

[DRC PDCN-2714] GTXE2_CHANNEL_valid_IBUFDS_GT_connection: GTXE2_CHANNEL dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt0_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i uses multiple REFCLK pins which prevents pin swapping and is driven by an IBUFDS_GTE2 dp_ss_i/vid_phy_controller_0/inst/gt_usrclk_source/gen_standard_clocking.ibufds_instQ0_CLK1 which as placed does not connect to the chosen REFCLK pin dp_ss_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/dp_ss_vid_phy_controller_0_0_gtwrapper_i/gt0_dp_ss_vid_phy_controller_0_0_gtwrapper_i/gtxe2_i/GTREFCLK1. Either use a single REFCLK so pin swapping can select a valid pin, or change the IBUFDS_GTE2 placement, or use a REFCLK pin (GTREFCLK0) which matchs the IBUFDS_GTE2 placement.

There are my project tcl and XDC files.
GTX pins are assigned in the same bank, is something I ignored?

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florentw
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149 Views
Registered: ‎11-09-2015

Hi @TonyWu_Wonder 

The issue is happening because you have placed mgtrefclk1 in a different bank than the one for the transceivers. You have 2 options:

  1. You are not planning to use mgtrefclk1 (only mgtrefclk0), then just connect mgtrefclk1 to GND:
    DP1.JPG
  2. If you are planning to use the mgtrefclk1, then you need to enable the Advanced Clock Mode in the Video Phy and connect the mgtrefclk1 to the correct clock pin (you need to use SOUTH or NORTH if coming from a different quad). Note that in advanced mode you also need to manually instantiate the BUFG_GTs

    DP2.JPG

    DP3.JPG

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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View solution in original post

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florentw
Moderator
Moderator
150 Views
Registered: ‎11-09-2015

Hi @TonyWu_Wonder 

The issue is happening because you have placed mgtrefclk1 in a different bank than the one for the transceivers. You have 2 options:

  1. You are not planning to use mgtrefclk1 (only mgtrefclk0), then just connect mgtrefclk1 to GND:
    DP1.JPG
  2. If you are planning to use the mgtrefclk1, then you need to enable the Advanced Clock Mode in the Video Phy and connect the mgtrefclk1 to the correct clock pin (you need to use SOUTH or NORTH if coming from a different quad). Note that in advanced mode you also need to manually instantiate the BUFG_GTs

    DP2.JPG

    DP3.JPG

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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