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Visitor
Visitor
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Registered: ‎06-08-2020

[DRC REQP-61] How can I connect 'clk_hs_rxp/rxn' to MIPI DPHY Rx IP?

Hi,

I’m using the MIPI DPHY Rx IP and got a DRC errors like below.

 

  • [DRC REQP-61] ibufds_connects_I_active: IBUFDS U_CORE_TOP/U_PHY_FPGA/inst/inst/mipi_dphy_0_rx_support_i/slave_rx.mipi_dphy_0_rx_ioi_i/ibufds_clk_inst pin I has an invalid driver U2_CLK_GEN/inst/mmcm_adv_inst
  • [DRC REQP-62] ibufds_connects_IB_active: IBUFDS U_CORE_TOP/U_PHY_FPGA/inst/inst/mipi_dphy_0_rx_support_i/slave_rx.mipi_dphy_0_rx_ioi_i/ibufds_clk_inst pin IB has an invalid driver U2_CLK_GEN/inst/mmcm_adv_inst

 mipi dphy.jpg

 

Connection of ‘clk_hs_rxp/clk_hs_rxn’ causes DRC error.

MMCM is used to receive ‘clk_hs_rxp/clk_hs_rxn’ now.

When 'clk_hs_rxp/rxn' are connected to MIPI DPHY Rx IP directly, pin assignment is disappeared.

Using ‘IBUFDS_DIFF_OUT ‘ has a similar error.

How can I connect 'clk_hs_rxp/rxn' to MIPI DPHY Rx IP?

 

Thank you for your help in advance.

JJ

 

<condition>

- FPGA: Kintex 7

- Vivado: 2018.3

- I_HS_CKP/I_HS_CKN : from MC20901(meticom)

- MMCM

clk_wiz_1 U2_CLK_GEN

   (

    .clkfb_in(clkfb_out),     // input clkfb_in

    // Clock out ports

    .clk_out1(HS_CKP),     // output clk_out1

    .clk_out2(HS_CKN),     // output clk_out2

    .clkfb_out(clkfb_out),    // output clkfb_out

    // Status and control signals

    .resetn(1'b1), // input resetn

    .locked( ),       // output locked

   // Clock in ports

    .clk_in1_p(I_HS_CKP),    // input clk_in1_p

    .clk_in1_n(I_HS_CKN));    // input clk_in1_n

 

 (HS_CKP: no buffer, HS_CKN: phase 180 degree, no buffer)

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5 Replies
Visitor
Visitor
371 Views
Registered: ‎06-08-2020

I found I_HS_CKP/CKN are not SRCC/MRCC pins. (pg202, page 84)
Is there any way to use MIPI DPHY Rx IP?
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Xilinx Employee
Xilinx Employee
298 Views
Registered: ‎03-30-2016

Hello @jjlim 

Since you are using 7-series device, you need to use SRCC/MRCC pins for D-PHY clock lane. (as mentioned in PG202)
Are you saying that you cannot use SRCC/MRCC pins on your board ??
MIPI_DPHY_pin_assignment.png


Kind regards
Leo

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Visitor
Visitor
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Registered: ‎06-08-2020

Hello Leo.

Yes. clk_hs_rxp/rxn are connected to user I/O in the board.
I'd like to check if I can use D-PHY IP in this situation before PCB revision.

Thank you for your help.
JJ

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Xilinx Employee
Xilinx Employee
211 Views
Registered: ‎03-30-2016

Hello JJ @jjlim 

Unfortunately no, without using SRCC/MRCC pins MIPI D-PHY IP will not be implementable.
For pin-assignment checking, We do suggest users to create a small test design and run implementation with Vivado before making the board.

Kind regards
Leo

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Visitor
Visitor
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Registered: ‎06-08-2020

Hello Leo

 

Thank you for your information and advice.

I will follow your guide.

 

Best regards

JJ