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kailassenan
Observer
Observer
20,836 Views
Registered: ‎01-22-2008

DVI/HDMI Video Receiver IP

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Hello Xilinx rep,

When would be your release of DVI/HDMI Video Receiver IP (XAPP460 and design files)?

I required the core for designing the DVI Receiver in the Xilinx Reference Design  http://www.xilinx.com/support/documentation/application_notes/xapp928.pdf

Kindly let me know regarding this.

 

Kailas Senan

Message Edited by kailassenan on 07-25-2008 12:47 AM
Spartan3_video_lnT.jpg
Spartan3_video_lnT.jpg
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bob.feng
Xilinx Employee
Xilinx Employee
21,868 Views
Registered: ‎07-29-2008
http://www.xilinx.com/support/documentation/application_notes/xapp460.pdf

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bob.feng
Xilinx Employee
Xilinx Employee
21,869 Views
Registered: ‎07-29-2008
http://www.xilinx.com/support/documentation/application_notes/xapp460.pdf

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kailassenan
Observer
Observer
20,759 Views
Registered: ‎01-22-2008

Hello Mr Bob Fen,

Thankyou for your reply.

Regards

Kailas Senan

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18,985 Views
Registered: ‎10-21-2008

Hello Bob,

 

I am evaluating DVI/HDMI Video Receiver IP and in this regard need clarification related to phasealigner.v.

 

Test Inputs: Test bench is driving TMDS_CLK clock at 74.25MHz and half clock data pattern is generated at a rate of 7.425 MHz.

 

From simulations I observe that, psaligned never gets set, as PSALGND state is never attained. Ultimately HSYNC, VSYNC and DE signals are been affected. Please let me know if I am wrong in driving clock or test pattern and suggest to clarify input conditions to set psaligned.

 

Thanks,

Ganesh.R

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Newbie
Newbie
17,810 Views
Registered: ‎09-13-2008

Hello! I downloaded the .pdf and reference files, but I'm unable to identify the spartan 3A TMDS evaluation and expansion boards shown at page 29.

 

Are them available for purchase and/or did you carry out your tests on another board?

 

Thanks a lot and Best Regards

Alessandro

 

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dhinu1
Visitor
Visitor
16,993 Views
Registered: ‎02-19-2009

Hello Bob,

 

I am pleased to see the reference design working in our boards. but i have a query regarding the reference designs whether the reference design works for all resolutions?

 

Because I am able to get Display control signals Hsnyc V Sync and Data en exactly for 40MHz Pixel clock. But as the Pixl clock increase to different resolutions say 110 Mhz pixel clock. the control signal are not generated.

 

I amusing SPARTAN 3AN FPGA: So please let me know if there are any customised Changes required in our Design. In the reference design the CLKIN period for the DCM is 13, so i assume  the  the expected Input frequency is around 70Mhz Pixel clock?? will it not work for other frequencies..

 

Thank you

Dhi

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15071976
Newbie
Newbie
13,189 Views
Registered: ‎07-09-2009

Dear Bob,

 

is a resolution of 1080p@50Hz/60Hz also possible with this design?

 

Regards,

Bjoern Thomas 

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