Data Integration issue with XIlinx UHDSDI IP example design (Xapp1248)
I am using a Kintex Ultrascale FPGA Board (KCU105) along with a Inrevium 12GSDI FMC card (TB-FMCH-12GSDI) to display 10 bit 1080p and 4K video through SDI. Xilinx UHDSDI example design (xapp1248) is taken as reference to integrate the SDI with my project. When I am integrating the example design with my design, the output is not getting locked (SDI mode lock) properly. The output data keeps coming and going.
We were able to recreate the issue in the Example project (xapp1248). Instead of test pattern, we are passing " free running counter" as data. The timing signals are same as test pattern. We are getting SDI output in test pattern but when it is replaced with counter, the output link is not stable.