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Registered: ‎01-09-2019

Data Secure Privileged issue on axi4lite port (IP DisplayPort TX subsystem)

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Hello,

I'm evaluating Xilinx's DisplayPort TX subsystem but A53 can't access to the axi4lite configuration interface (all other axi4lite work correclty : phy_controller, clk_wiz, vdma,...).

DPTXSS IP is composed of a xbar which swicthes axi4lite between an internal VTC module and DisplayPort module (see attached dptxss_bd.png).

I have implemented another VTC in my design and A53 can ping the version register (see attached XCST console picture @mrd 0xA0050010).

Unfortunately, the VTC inside the DPTXSS IP fails (see attached XCST console picture @mrd 0xA0041010)

ila debugger shows a "Data Secure Priviledged" on ARPROT then RRESP = DECERR (see attached trace mrd0xA0041010)

Could you please help me to understand this issue ? How can A53 access to the configurations ports?

Thank you in advance for your help.

Hervé

 

mrd0xA0040010.PNG
xsctConsole_addressEditor.PNG
dptxss_bd.PNG
mrd0xA0041010.PNG
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Moderator
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Registered: ‎11-09-2015

Hi herve.langlais@technicatome.com ,

Could you give me some details about your design:

  • what vivado version are you using?
  • Is the DP SS IP connected through an AXI interconnect or an AXI Smartconnect.

I already saw a similar issue. I was not really able to explain what went wrong in the design. The example design for the DP IP on ZCU102 is usually working fine.

The workaround was to use the AXI Smartconnect instead of the AXI interconnect between the processor and the DP IP.

But also, please try with 2018.3.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
576 Views
Registered: ‎11-09-2015

Hi herve.langlais@technicatome.com ,

Could you give me some details about your design:

  • what vivado version are you using?
  • Is the DP SS IP connected through an AXI interconnect or an AXI Smartconnect.

I already saw a similar issue. I was not really able to explain what went wrong in the design. The example design for the DP IP on ZCU102 is usually working fine.

The workaround was to use the AXI Smartconnect instead of the AXI interconnect between the processor and the DP IP.

But also, please try with 2018.3.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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556 Views
Registered: ‎01-09-2019

Hi,

I use vivado 2018.3.

Indeed, the issue seems to come from AXI interconnect and the XBAR in the DP IP.

The issue is solved if smartconnect is instantiated instead of AXI interconnect (strange, no?)

Thank you for your help

 

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Moderator
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Registered: ‎11-09-2015

Hi herve.langlais@technicatome.com ,

In fact, looking back at the debug cases I had previously, it seems that the smartconnect is only masking the issue.

Can you refer to pg233 p26:

dp.JPG

Can you make sure the above conditions are applied in your design?

This is for RX but the same might apply to TX.

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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