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Observer
Observer
1,777 Views
Registered: ‎06-19-2018

Deinterlacer Algorithm Selection

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Hi,

           I am working on VPSS based Deinterlacer. I configured VPSS in Deinterlacer mode only with Motion Detection Algorithm. As per PG231 datasheet of the VPSS, it supports six algorithms.But in the xvprocss driver level there is no function to select an algorithm and i saw the register description of the Deinterlacer which has register 0x38 [7:0] to select an algorithm. 

My question is : How to select different algorithms in 0x38? 

          I want to configure the Deinterlacer in Motion Detection Algorithm in the Software Level.

        

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Moderator
Moderator
1,398 Views
Registered: ‎11-09-2015

HI @rahul_gs, @dukbru, @ajaykumargurrala,

 

Clarification:

 

The VPSS driver will select the best algorithm depending on your HW configuration during the configuration of the VPSS (not changing while running).

The algorithm can be selected using the API XV_deinterlacer_Set_algo from the user application before calling the start_system() API.

In memory based mode (adaptive motion deinterlacer enabled), you can select all the 6 different algos, but mode 0 is median which is highest quality for most content.
If you want to select a different algorithm it will be as follow:
0-median, 1-Bob, 2-Weave, 3- Vertical Temporal Linear Interpolation, 4- Vertical Temporal Median, 6-passthrough (Bilinear)

In non-memory mode, the only thing you can do is spatially interpolate  lines. There are 2 algorithms: 1 is bob, and 0 is again highest quality but in this case that means we do a linear interpolation instead of bob.

This is basically what you read in reg 0x38 (note that we do not recommend to access registers directly).

 

Hope that helps,

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
1,738 Views
Registered: ‎11-09-2015

HI @rahul_gs,

 

It is not possible to change the algorithm manually yet. The VPSS will automatically select the best algorithm depending on the HW configuration.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
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Registered: ‎07-05-2018

Hi @florentw,

 

I'm running into the same issue.

So any insight in when this algorithm control will be available?

This control is important to me to be able to limit the memory usages for example when having multiple vpss deinterlacers to use more video channels. So the best effort automatic version is unwanted/unacceptable behavior for me.

 

Kind Regards,

Dukbru

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Moderator
Moderator
1,682 Views
Registered: ‎11-09-2015

HI @dukbru,

 

This is not an issue but a limitation from the core.

 

This as been requested but I cannot give any release date


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
1,638 Views
Registered: ‎11-09-2015

Hi @rahul_gs

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎08-26-2017

Hi Florent,

 

The auto selection of Algo's based on inputs is something which is not very clear. 

 

There are only two inputs to deinterlacer , one is the output frame size and the other is the Motion Based Deint enable/disble. 

 

Output frame size cannot be used to decide an algo as all algos are intended to give same output frame size. 

 

Coming to Motion Based Deint enable/disable, there are three algos which are motion based and 3 which are not motion based. 

 

Now, assuming motion based is enabled, how will the IP/SW select one of the three options available? Same is the case when motion based is disable, how will the IP/SW select between BOB/WEAVE/LINEDOUBLING? Each of these are bound to give same output size (but different quality)

 

If we can get these details that are used by SW/IP to select the algo, we will be able to create that particular environment.

 

Thanks and Regards,

Ajay Kumar G

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @ajaykumargurrala,

 

The IP should select the algo based on the IP configuration


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
1,544 Views
Registered: ‎11-09-2015

Hi @rahul_gs

 

This topic is still open and is waiting for you.

If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
1,399 Views
Registered: ‎11-09-2015

HI @rahul_gs, @dukbru, @ajaykumargurrala,

 

Clarification:

 

The VPSS driver will select the best algorithm depending on your HW configuration during the configuration of the VPSS (not changing while running).

The algorithm can be selected using the API XV_deinterlacer_Set_algo from the user application before calling the start_system() API.

In memory based mode (adaptive motion deinterlacer enabled), you can select all the 6 different algos, but mode 0 is median which is highest quality for most content.
If you want to select a different algorithm it will be as follow:
0-median, 1-Bob, 2-Weave, 3- Vertical Temporal Linear Interpolation, 4- Vertical Temporal Median, 6-passthrough (Bilinear)

In non-memory mode, the only thing you can do is spatially interpolate  lines. There are 2 algorithms: 1 is bob, and 0 is again highest quality but in this case that means we do a linear interpolation instead of bob.

This is basically what you read in reg 0x38 (note that we do not recommend to access registers directly).

 

Hope that helps,

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post