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deepakb
Contributor
Contributor
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Registered: ‎08-07-2013

Difference between VDMA and frame buffer write and read IPs implementation

Hello,

I wanted to understand the technical difference w.r.t implementation of DMA and frame buffer write and read IPs.

I am aware of the below answer record which explains when to use the VDMA and when to use the frame buffer write and read IPs.

https://www.xilinx.com/support/answers/72543.html 

What I am trying to understand here is that, in case of HDMI pass though design, how many buffers are considered in frame writer and read IP? Xilinx document mentions that genlock has to be taken care by the user. So I expect that example design doesn't implement the genlock and due to this reason I am thinking only one buffer is used instead of multiple buffers.

Is my understanding is right? If yes, then how frame writer is writing to one buffer and frame read is reading from same buffer? Also with single buffer whether we will be able to take care the frame rate difference? Something like input is 4K@60 and output is 4K@30. Whether one buffer is sufficient in case of VDMA as well for handling the different frame rates?

Thank you in advance.

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reaiken
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Registered: ‎07-18-2011

@deepakb 

In the frame buffer write/read IPs, you reconfigure the buffer address manually every time in the interrupt service routine, so you control the number of buffers by how many different addresses you use. 

You also control the frame synchronization by determining which of your buffer addresses to read or write to, and dropping/repeating a buffer based on which buffer the other one is using.

For example,  if you want the write side to be the master and the read side to be the slave, you let the frame buffer write  IP cycle through 3 buffer addresses,  changing the address every time the interrupt occurs.  Then, in the frame buffer read interrupt service routine, you first check the current write address and make a determination to either increment the read address, skip an address, or repeat the address if it would result in writing to the same address the write side is using.  The goal is to maintain the read address at an average constant one frame delay behind the write address.    You could also do variations on this, similar to the dynamic master operation of the VDMA.

Basically,  the VDMA and frame buffer read/write are similar in function,  but the frame buffer read/write puts you in control of everything in software,  while the VDMA is set up once and runs autonomously.

Normally, you would want to use 3 buffers for frame synchronization or frame rate conversion.  A single buffer would result in "tearing " artifacts as the read and write sides cross over. 

The exception to this would be if the read and write sides are on the same clock and same frame rate, as they could be in a pass-through implementation, where you can simply offset the read and write sides by half a frame or so, since they will never cross over each other. This is basically a FIFO implementation and a frame buffer is not really needed,  unless you want to implement something like freeze functions or a synchronized memory overlay.

deepakb
Contributor
Contributor
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Registered: ‎08-07-2013

@reaiken ,

Thank you for your detailed response.

So the summary is that, for same frame rate, we can use single buffer with slight offset so that both write and read will not cross over and for different frame rates, we need to use multiple buffers typically 3. Correct?

Is this same for both VDMA and frame writer and reader? I mean can VDMA also will work with single buffer for same frame rate? In other words, frame writer and reader have some other way of implementation to take care same frame rate using single buffer which is not available in VDMA.

Also is it possible to write from single frame writer and read same buffer (one or more) from multiple frame readers if the use case is having single input video to be presented on multiple output displays?

Thank you in advance.

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reaiken
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Registered: ‎07-18-2011

@deepakb 

Not quite. 

If you are doing a pass-through design, where the output is clocked from the recovered input clock, and the format is the same, you can do a single-buffer implementation, or no frame buffer at all. The only instance where you would need a frame buffer in a pass-through implementation would be if you wanted to freeze the pass-through image  or add a graphics or character overlay that is read from memory.  Even then, if the graphics or characters are done with a pixel switch locked to the incoming H and V, you wouldn't need a frame buffer.

Any other implementation,  such as frame rate conversion, or even if the input and output frame rates are identical,  but the output clock is not locked to the input clock, would require a triple-buffer memory.  Just because the input and output clock rates are the same doesn't mean they are synchronous,  they will slowly change with respect to each other and you will see image tearing as a result. 

So,  if you are just doing a pass-through,  you don't need any memory as long as the output clock is the same clock as the recovered input clock.  Anything else requires frame synchronization. 

Yes, you can use one frame buffer write IP and multiple frame buffer read IPs (or VDMAs) that access the same write buffers, as long as you control the frame synchronization to insure none of them are reading from the same buffer the write side is accessing.   

However, if all the read sides are synchronous and all outputs are the same,  you only need one frame buffer read IP.  You can use the AXI-stream broadcaster IP to split the output into multiple streams. Just be aware that if you stop any one of them, it will stop all of the paths.  In practice,  this is not usually a problem, as the read sides run continuously unless you issue a reset to one of them.