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auricm
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Registered: ‎06-13-2012

DisplayPort Edid

Hi all,

 

I'm trying to work with the Displayport IP, specifically with receiver and the example design made over KC705, customizing the cote to fit custom board.
With oscilloscope I see that as I plug the source the aux channel start the communication and the core start the configuration of DP159.
But the source seems to be unable to read the sink EDID so I started investigate on it.

The load_EDID has the following code

int j;
int i;
u8 edid[256] = { 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x61, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x19, 0x01, 0x04, 0xB5, 0x3C, 0x22, 0x78, 0x3A, 0x4D, 0xD5, 0xA7, 0x55, 0x4A, 0x9D, 0x24, 0x0E, 0x50, 0x54, 0xBF, 0xEF, 0x00, 0xD1, 0xC0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xB3, 0x00, 0x71, 0x4F, 0x81, 0xC0, 0x01, 0x01, 0x4D, 0xD0, 0x00, 0xA0, 0xF0, 0x70, 0x3E, 0x80, 0x30, 0x20, 0x35, 0x00, 0x54, 0x4F, 0x21, 0x00, 0x00, 0x1A, 0x04, 0x74, 0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58, 0x8A, 0x00, 0x54, 0x4F, 0x21, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0xFD, 0x00, 0x1D, 0x50, 0x18, 0xA0, 0x3C, 0x04, 0x11, 0x00, 0xF0, 0xF8, 0x38, 0xF0, 0x3C, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x58, 0x49, 0x4C, 0x49, 0x4E, 0x58, 0x20, 0x44, 0x50, 0x0A, 0x20, 0x20, 0x20, 0x01, 0x19, 0x02, 0x03, 0x27, 0x71, 0x4F, 0x01, 0x02, 0x03, 0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x1F, 0x90, 0x0E, 0x0F, 0x1D, 0x1E, 0x23, 0x09, 0x17, 0x07, 0x83, 0x01, 0x00, 0x00, 0x6A, 0x03, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x78, 0x20, 0x00, 0x00, 0x56, 0x5E, 0x00, 0xA0, 0xA0, 0xA0, 0x29, 0x50, 0x30, 0x20, 0x35, 0x00, 0x54, 0x4F, 0x21, 0x00, 0x00, 0x1E, 0xE2, 0x68, 0x00, 0xA0, 0xA0, 0x40, 0x2E, 0x60, 0x30, 0x20, 0x36, 0x00, 0x54, 0x4F, 0x21, 0x00, 0x00, 0x1A, 0x01, 0x1D, 0x00, 0xBC, 0x52, 0xD0, 0x1E, 0x20, 0xB8, 0x28, 0x55, 0x40, 0x54, 0x4F, 0x21, 0x00, 0x00, 0x1E, 0x8C, 0x0A, 0xD0, 0x90, 0x20, 0x40, 0x31, 0x20, 0x0C, 0x40, 0x55, 0x00, 0x54, 0x4F, 0x21, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0 }; for(i=0;i<(256*4);i=i+(16*4)){ for(j=i;j<(i+(16*4));j=j+4){ XDp_WriteReg (XPAR_DP_RX_HIER_VID_EDID_0_BASEADDR, j, edid[(i/4)+1]); } } for(i=0;i<(256*4);i=i+4){ XDp_WriteReg (XPAR_DP_RX_HIER_VID_EDID_0_BASEADDR, i, edid[i/4]); }

 

I don't understand the two "for" instructions but what I found strange is that with the debugger I see the function  "XDp_WriteReg" write the data in two (or more) different address in the same time. So there's a problem with the debugger or with the function???

I expect that the function must write data in a single address.
Obviously if I write the same data in different places it happens that I overwrite previously written data.

Regards

 

 

 

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11 Replies
florentw
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Registered: ‎11-09-2015

HI @auricm,

 

I am not sure why there is 2 different addresses. It might be how the EDID block was coded.

 

However, I would not expect to have write of the same data at multiple addresses. Could you give details on what you see on the debugger?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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auricm
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Registered: ‎06-13-2012

Hi @florentw,

 

here's a screenshot of debugger, I changed the instruction XDp_WriteReg with Xil_Out32

debugX.jpg

You can see in the memory window the red values change with a single write.
Actually I moved my attention to the edid block I download from Xilinx AR#68629

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florentw
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Registered: ‎11-09-2015

Hi @auricm,

 

It seems to be the correct value as per the EDID... Could you just dump the memory after the all the write operations and see if all the data are expected?

 

Note, I wouldn't use Xilinx AR#68629 unless you really require it.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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auricm
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Registered: ‎06-13-2012

@florentw

 

I've attached the memory dump after complete write.
The data is not as I expected, it's different from the source u8 Edid[256]

 

I used AR#68629 as I need the edid and I'm not able to use the Video_edid IP present in the examples design of Displayport.

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florentw
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Registered: ‎11-09-2015

Hi @auricm,

 

I do not see any 0xFF. DOes it means that the 0XFF you see with the debugger gets overwritten?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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auricm
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Registered: ‎06-13-2012

Hi @florentw,

 

yes, 0xFF gets overwritten, in a single instruction two address are written, it writes up to the 127th byte in the correct order, then start again from position 0 (address 0x44A20000) and overwrite previous data. So in the first address position I find the second half of the edid vector.




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florentw
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Registered: ‎11-09-2015

Hi @auricm,

 

Did you try directly with the example design with a Xilinx board? Do you get the same behavior?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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auricm
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Registered: ‎06-13-2012

Hi @florentw,

 

I'm working with a custom board and I don't have a Xilinx board to try example design.

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florentw
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Registered: ‎11-09-2015

Hi @auricm,

 

Just to follow up on this, were you able to make progress? Do you have a solution to share with the community?

 

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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auricm
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Hi @florentw,

 

no progress on that, I modify the default values in the original file and avoid write/read the EDID values in the firmware.

Regards

Thanks for support


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florentw
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Registered: ‎11-09-2015

HI @auricm,

 

Thanks for the update. Not sure what is the issue here. I have never sen the issue on the example designs...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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