10-19-2020 11:12 AM
I am attempting to implement a bridging solution for DisplayPort to MIPI-DSI. I found the following IP's:
Here are my questions
1- Would it be possible to use these IP's to implement DP to DSI?
2- Are there any available designs doing this?
3- I am looking at the Zynq-7000 SoC because it supports both IP's and is affordable. Is that a good choice?
10-19-2020 02:29 PM
>3- I am looking at the Zynq-7000 SoC because it supports both IP's and is affordable. Is that a good choice?
What is your target resolution ?
It depends on your requirement.
10-20-2020 12:34 AM
Just adding my two cents.
Yes you can you both IP to implement DisplayPort to MIPI DSI TX.
# For MIPI DSI TX reference design, please see PG232 Chapter 5.
You can configure the Example Design to target ZCU102,SP701 or VCK190.
All Example Design has MIPI CSI-2 RX --> MIPI DSI TX implementation.
Probably you can generate an Example Design for SP701 for a reference.
# Please notice that if your DSI panel needs DCS long packet support for register configuration,
You need to use MIPI DSI TX from Vivado 2019.2 or newer version.
10-20-2020 02:12 AM
One caution about displayport on Zynq-7000:
The displayport IP does not support all the Zynq-7000 devices. Only the ones with GTX (kintex-7 based fabric) are supported (i.e Z-7030, Z-7035, Z-7045, Z-7100).
Also with Zynq-7000 for MIPI you need to have an external phy as per xapp894. This is not required in UltraScale+.
Thus Zynq Ultrascale+ might be something to consider. There is an example design for Displayport RX (using an external FMC card) and another example for MIPI DSI (as @karnanl mentioned, also requiring a FMC card) both running on the ZCU102. So this gives a good starting point.
Of course this is more expensive. I am not in sales so not trying to have you buy the most expensive. I am just mentioning it because it should be faster to develop (so you might save some engineering resources).
10-20-2020 07:46 AM
10-20-2020 08:00 AM
Thanks a lot. This is valuable information. Currently I am setting up the display using short packets. Does the the IP support DCS short packets as well?
I also need to do DP to dual MIPI using MST, each display is 1080x2160 @60Hz. Can I implement that witih the Z-7030?
10-20-2020 08:36 AM
GTX is a gigabit transceiver correct? Could this be implemented on the low-cost z-7000 devices using an external IC? The Z-7030 is already started to get too expensive for our application.
10-20-2020 09:04 AM
Yes GTX is a gigabit transceiver. This is required for the Xilinx Displayport IP.
There might be external to do "Displayport to data lanes" ICs but I am not knowledgeable about this so you will have to look around.
10-20-2020 02:24 PM
>Would that be possible on the zynq-7000?
I guess you can achieve what you want to do.
However, you must use HBR2 (5.4Gbps) x 4 lane on your device, if color format is RGB888.
Also, you might need to consider external retimer or redriver to correctly receive signals.
As @florentw mentioned before, you can refer display port example design for KC705.
10-20-2020 09:33 PM
Regarding MIPI DSI TX Subsystem IP.
> Does the the IP support DCS short packets as well?
Yes. This IP support DCS short write command also. Please see PG238 Chapter 1,2.
( DCS read command is not supported )