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Participant
Participant
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Registered: ‎06-22-2017

Displayport 1.4 example in vivado 2019.1

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Hi,

I use KCU105 platform and try to generate displayport 1.4 pass-through example in vivado 2019.1,

but it failed when generating ip output product, the error messages said that v_axi4s_remap ip are not found.

 

Then I add a IP repositories to ./Xilinx/Vivado/2019.1/data

but still can't solve it.

 

please help, thanks!

 

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Moderator
Moderator
666 Views
Registered: ‎11-09-2015

Hi @furball 

This is a quote of the guidelines for the video board on the Xilinx forums:

Before you post a question:

    Ensure you have read the Product Guide for the IP
    Search the Xilinx Knowledge Base for known issues.
    Search on the forums for similar topics

 

You might want to look for similar question before posting as it can save you some time.

The exact same question was asked last week:

https://forums.xilinx.com/t5/Video/Displayport1-4-MST-example-design-synthesis-failed/td-p/983285

This is probably due to the path length under windows

Hope that helps


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Moderator
Moderator
667 Views
Registered: ‎11-09-2015

Hi @furball 

This is a quote of the guidelines for the video board on the Xilinx forums:

Before you post a question:

    Ensure you have read the Product Guide for the IP
    Search the Xilinx Knowledge Base for known issues.
    Search on the forums for similar topics

 

You might want to look for similar question before posting as it can save you some time.

The exact same question was asked last week:

https://forums.xilinx.com/t5/Video/Displayport1-4-MST-example-design-synthesis-failed/td-p/983285

This is probably due to the path length under windows

Hope that helps


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Participant
Participant
641 Views
Registered: ‎06-22-2017

sorry, i missed that post.

but i thought xilinx already fixed the windows path length issue since 2018.3. 

 

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Moderator
Moderator
634 Views
Registered: ‎11-09-2015

HI @furball 

Did you try to use a realy short path (i.e. build the example design on the root of your drive)? Xilinx only have reduced the length of the example design. The limitation is a windows limitation, thus Xilinx cannot fix it.

As per the AR:

Note: the path length of the example design project will be reduced in the 2018.3 release. The user will just need to select a short directory to build the example design into.

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Highlighted
Moderator
Moderator
611 Views
Registered: ‎11-09-2015

HI @furball 

Did you try to reduce the path? I tried to open the example design on my windows machine, under C:/DP and it is working fine for me


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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