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Visitor
Visitor
639 Views
Registered: ‎02-06-2019

Displayport RX problem with MSA registers

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Hi!

I am working with the DisplayPort IP block and configuring it as  sink core (the DisplayPort v7.0) with  2 lanes. 2 lanes are trained.

I successfully transfer images from my TX part to the sink core without scrambling. The main stream attributes packet is OK. Reading the MSA registers (0×500 - 0×538), I see the values that I set for the TX transmitter.

But when I enable scrambling on the both sides I get strange result:

— Image is being transmitted correctly ();

— the value for MSA registers  received on 0 lane are correct, but the MSA registers received on 1 lane are not correct (I get MSA_NVID = 009C7133, but expect MSA_NVID = 00800000).

I transfer next image: 640×480×75Hz.

----

Why the attributes packet transmitted on 1 line is not correctly recognized by DP Sink core when scrambler is enabled ?

What I did wrong ?

 

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Teacher
Teacher
562 Views
Registered: ‎06-16-2013

Hi @aubogdan 

 

Is your mentioned about simulation ?

If yes, you turn on inter skew function on DP Tx.

Because it's link training issue during inter skew adjustment.

 

If no, I suggest you to consider your schematic.

 

And, I mentioned again.

This IP is obsoluted. I strongly suggest you to use latest DP Rx IP.

 

Best regards,

View solution in original post

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Teacher
Teacher
602 Views
Registered: ‎06-16-2013

Hi @aubogdan 

 

First of all, I strongly suggest you to latest Xilinx DP Rx IP.

Because you mentioend DP Rx IP is obsoleted.

 

BTW, what do you mean "scrambling" ?

Do you use HDCP ?

If yes, you need to implement HDCP core.

 

If no, it seems SSC issue.

How much percentage do you use for SSC ? Is it under specification of DP ?

 

Best regards,

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Visitor
Visitor
584 Views
Registered: ‎02-06-2019

Hi, @watari 

I do not use HDCP.

Under scrambling, I mean next:

DPCD_SCRAMBLING_DISABLE. Value of the scrambling disable field of the DPCD
training pattern register. By default, scrambling is disabled.
• [0] – Set to 1 when the transmitter has disabled the scrambler and transmits all
symbols.

What is a SSC ?

----

Thank you I will try to use the latest version of Xilinx DP Rx IP.

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Teacher
Teacher
579 Views
Registered: ‎06-16-2013

Hi @aubogdan 

 

How do you connect DP signal between source and sink ?

Do you use DP retimer between them ?

Also what link rate do you use ?

 

It seems link training issue.

 

BTW, as I already mentioned before, I strongly suggest you to use latest DP Rx IP.

What you use DP Rx IP is obsoluted.

 

Best regards,

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Visitor
Visitor
570 Views
Registered: ‎02-06-2019

1. "How do you connect DP signal between source and sink ?"

displayport_rx_2x u_displayport_rx_2x (

...

.lnk_rx_lane_p ({gt1_gtxtxp,gt0_gtxtxp} ),
.lnk_rx_lane_n ({gt1_gtxtxn,gt0_gtxtxn} ),

)

2. "Do you use DP retimer between them ? "

What do you mean ?

3." Also what link rate do you use ?" I use 1.62 Gb/s.

--

I think it is not link training issue. Because 2 lanes are trained and I successfully transfer my dates.

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Highlighted
Teacher
Teacher
563 Views
Registered: ‎06-16-2013

Hi @aubogdan 

 

Is your mentioned about simulation ?

If yes, you turn on inter skew function on DP Tx.

Because it's link training issue during inter skew adjustment.

 

If no, I suggest you to consider your schematic.

 

And, I mentioned again.

This IP is obsoluted. I strongly suggest you to use latest DP Rx IP.

 

Best regards,

View solution in original post

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Highlighted
Visitor
Visitor
532 Views
Registered: ‎02-06-2019

Hi @watari 

I am speaking about the simulation.

At first, I will try to use the latest version of DP RX IP from Xilinx.

Thank you!

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Moderator
Moderator
529 Views
Registered: ‎11-09-2015

Hi @aubogdan 

As mentioned by @watari you should move to the displayport subsystem IP.

However note that simulation is not supported for the displayport subsystem IP.

You will only get support from Xilinx if you can reproduce this issue on HW.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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