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Observer
Observer
1,166 Views
Registered: ‎06-05-2018

Displayport Subsystem IP not supported on Artix-7? Why not?

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I am designing a product which requires Displayport Tx and currently developing on Digilent's Nexys Video board, but none of the Xilinx Displayport Subsystem IP seems to be supported on Artix-7.

 

The Nexys Video board (with XC7A200T-1SBG484C) has the required GTP which should meet DP spec. even for DP1.3, and it is in fact routed to a mini-Displayport connector on the board.

 

Is there any possible way to implement this IP in my design?

 

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Moderator
Moderator
1,214 Views
Registered: ‎10-04-2017

Hi @tommymc,

 

The DisplayPort SubSystem does not support Artix-7 devices. Due to clocking, fabric, and density, I do not recommend using Artix devices for DP/HDMI cores.

 

If you choose to move forward with an Artix device, you may be able to add a DP Tx interface to your design. The DisplayPort 7.0 core (not SubSystem) was available Vivado 2017.2 and earlier. I believe that this core can target Artix devices. I do not recommend using discontinued IP

 

Without knowing your project requirements, my suggestion is to move to a Kintex device and use the DisplayPort SubSystem and the latest release of the Vivado tools.

 

Regards,

Sam

 

 

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

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Moderator
Moderator
1,215 Views
Registered: ‎10-04-2017

Hi @tommymc,

 

The DisplayPort SubSystem does not support Artix-7 devices. Due to clocking, fabric, and density, I do not recommend using Artix devices for DP/HDMI cores.

 

If you choose to move forward with an Artix device, you may be able to add a DP Tx interface to your design. The DisplayPort 7.0 core (not SubSystem) was available Vivado 2017.2 and earlier. I believe that this core can target Artix devices. I do not recommend using discontinued IP

 

Without knowing your project requirements, my suggestion is to move to a Kintex device and use the DisplayPort SubSystem and the latest release of the Vivado tools.

 

Regards,

Sam

 

 

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post