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Visitor
Visitor
8,117 Views
Registered: ‎09-10-2014

Displayport v4.2 Incomplete Documentation Issue

I’m trying to implement a displayport source core design on an ZC706 board. I’m using the Avnet DVI I/O FMC module which has a displayport tx interface. (http://avnetexpress.avnet.com/store/em/EMController/Development-Kits/Avnet-Design-Services-Custom/AES-FMC-DVI-G/_/R-10548840/A-10548840/An-0?action=part&catalogId=500201&langId=-1&storeId=500201) .

 

I’m trying to implement a hardware state machine based link policy maker to configure the link. I have a few questions regarding to the following PHY attributes listed in the Displayport source core datasheet (v4.2). The datasheet does not properly explain their function or how they should be configured for a particular implementation.

 

“PHY_VOLTAGE_DIFF_LANE_0 . Controls the differential voltage swing for lane 0 of the DisplayPort link. • [2:0] - Supports up to eight levels of voltage swing for a wide variety of PHY implementations.  The mapping of the four levels supported by the DisplayPort specification to the eight levels indicated here is implementation specific.”

 

“PHY_PRECURSOR_LANE_0. Set the pre-cursor level for lane 0 of the DisplayPort link. • [4:0] - Controls the pre-cursor level for lane 0 of the transmitter. The mapping of the four levels supported by the DisplayPort Standard to the 32 levels indicated here is implementation specific. Valid for 7 series FPGAs only.”

 

“PHY_POSTCURSOR_LANE_0. Set the post-cursor level for lane 0 of the DisplayPort link. • [4:0] - Controls the post-cursor level for lane 0 of the transmitter. The mapping of the four levels supported by the DisplayPort Standard to the 32 levels indicated here is implementation specific. Valid for 7 series FPGAs only.”

 

Does anybody know how these mapping actually happens. Where can one find any documentation relating to this.

Also the document does not specify the exact meaning of all the bits of the “PHY_STATUS” register. For example the bit pattern description of “Transmitter buffer status, lane 0” and “Transmitter error, lane 0” is not defined.

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Adventurer
Adventurer
7,949 Views
Registered: ‎01-29-2013

Unfortunately I can't help you, but in case you didn't know, the displayport ip core license costs $20,000USD. I thought about using this core for about 5 minutes until I saw the price.
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