02-02-2012 03:17 AM
So I'm having a problem with a small part of my design and the picture below shows where it is (it's part of a feedback line).
At the downsample(s) block's input I have a pulse with a width of 3 (ranging from 3358 to 3361 for instance) and with a sample time of 0.2 as shown in the "Legend".
I want to change that pulse such that I get a sample rate of 8 and I'm using a couple of Downsample blocks for it.
My problem is that each time I make changes in the main path of my design that involve delays and such, my pulse and disappears at this output.
Sometimes I inverse the order of the downsample blocks and it's there and sometimes it isn't. Also tried a Downsample by 40 block and the situation is the same.
Can anyone explain me why?
Any suggestions on how to deal with this problem permanently?
02-02-2012 06:01 AM
The purpose of Downsample block is decimation of input array (or stream).
If we have Downsample block with 'Sample rate' parameter set to 40, then after receiving of first 40 samples it will output only one sample (actually, first or last sample of input frame).
Lets consider following input stream:
x0, x1, x2, x3, ..., x39, x40, x41, ..., x79, x80, x81, ...
Output stream will be following (if we have set 'first value of frame'):
y0 = x0, y1 = x40, y2 = x80, ...
Or output stream will be following (if we have set 'last value of frame'):
y0 = x39, y1 = x79, ...
So your design is working as expected: due to short duration of your input pulse (only 3 samples vs downsampling coefficient = 40) and unknown location of this pulse, sometimes it can sample input pulse, sometimes it can't. Cascading of several downsampling blocks will not fix the problem.
Are you sure that you really need to downsample this signal? If answer is yes, then it's better to make custom block (for example, in VHDL) that scans input data for active level and outputs this level at lower sample rate (longer sample time).
02-02-2012 06:36 AM
Thanks for the answer vlavruhin.
I get it now.
The output go into a Counter with an explicit period so I'm assuming the sample rate is mandatory.
Well my VHDL knowledge is awful really and I'm much more comfortable doing it in SysGen.
Any ideas on how to do it?
Although the pulses at the input are periodic between themselves, the gap between initialization and the 1st pulse is not the same so I don't think a simple delay will do it.
Guess I gotta look into it. Any suggestions are appreciated.
02-03-2012 01:02 AM
Tiago, if you really need to implement it in System Generator, then there is a quick solution.
1) Cast input boolean pulse to 1-bit unsigned fixed-point signal (it can be done with 'Convert' block).
2) Use 'Serial to Parallel' block to convert input 1-bit stream to 40-bit output stream (with output_sample_time = 40 * input_sample_time).
3) Convert 40-bit stream to boolean signal (for example, using 'Relational' block to compare with zero constant).
06-03-2014 07:00 AM
I had the same problem as fruntxas and, therefore, I am glad that I found this solution which works pretty well. Nonetheless, the solution looks like a hack which is a little bit unsatisfying.
Is there a more convenient way to maintain the short impulse generated in the faster clock domain?
Personnally, I would use a shift register bank with 40 registers and I would connect the output of these registers to a 40 input OR block. The output of the OR block can then be registers in the slow clock domain in which the short impulse is now maintained. Is there a better way to do this? I just try to get better in DSP ;)
06-04-2014 01:51 AM
The Shift Register solution is nice and easy if the down sampled rate is low.
Some more solutions:
A) register the signal and reset once you read it in the downsampled frequency:
B) There is also the Reset Generator block, which i think can be used for that as well.
C) Use a counter to generate a 40 cycle long pulse and then down sample it
06-04-2014 03:27 AM
Wow! Thanks, Markus! That is exactly what I was looking for.
Do you know any literature (books, tutorials) from which I can get familiar with circuit designs like your solution A)?
06-04-2014 06:05 AM
unfortunately I dont have any literature I can recommend. The basics I learned in university the rest by trying. As a basic note: A counter block together with relational blocks driving its own reset/enable is your best friend for designing timing based circuits.
Be aware that my solution will ignore any additional pulses which appear within some cycles after one pulse is detected.
From your description however this seems not to matter.