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young1988
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Registered: ‎11-29-2017

Dual MIPI D-PHY RX core in one bank fail implementation

When I have two instances of MIPI D-PHY(4.0) RX IP with fixed calibration in one bank, the implementation failed.

Error message shows

[DRC PLIDC-4] IDELAYCTRL IODELAYs with conflicting groups for same bank: Found IODELAY cells with different IODELAY group constraints for same I/O bank 35. The IODELAY cells and its group constrained to this bank are: 'mipi_dphy_inst/inst/mipi_dphy_rx_support_i/slave_rx.mipi_dphy_rx_ioi_i/dl0_with_delay.idelaye2_bus_0 : mipi_dphy' 'mipi_dphy_inst2/inst/mipi_dphy_slv_rx_support_i/slave_rx.mipi_dphy_slv_rx_ioi_i/dl0_with_delay.idelaye2_bus_0 : mipi_dphy_slv' 

 

The envirioment is VIVADO 2017.3.1_AR69431(64bit), I fallowed the PG202, selected the option of "Include IDELAYCTRL in core" in one core. I have read the AR# 69441, but the problem still there, so can I get any help?

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florentw
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Registered: ‎11-09-2015

Hi @young1988,

 

As you are using 2 MIPI in the same bank I assume you have connected one as MASTER (Include Shared Logic in core) and the other as SLAVE (Include Shared Logic in example design)?

Could you make sure they are connected as mentioned in the PG202:

MIPI.PNG

 

And also, the option "Include Shared Logic in core" is not the same as "Include IDELAYCTRL in core". Make sure you have the correct configuration for the IP.

 

Regards,

 

Florent


Florent
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young1988
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I have two MIPI DPHY RX part, that means both of them are slave, so no shared logic option!

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florentw
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Hi @young1988,

 

I have two MIPI DPHY RX part, that means both of them are slave, so no shared logic option!

> No, you need to have one master and one slave even for RX. This is the way to have multiple instances in the same IO bank:

MIPI.PNG

 

 

So this is why the implementation is failing. You need to set one master:

MIPI2.PNG


Florent
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young1988
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Sorry I forgot say the device is Zynq7020(xc7z020clg400-2), the RX core don not have a shared logic option...is it only UltraScale+ devices have the shared logic options in RX?

 

 

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florentw
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HI @young1988,

 

Oh yes sorry this is not applicable for 7-series as there is no PLL or MMCM inside the DPHY RX.

 

Could you give detail on your constraints?

 

Regards,

 

Florent

 

 


Florent
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young1988
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OK! the hardware design followed the xapp894.

 

## dphy cmos1
# dphy compatible solution from xapp894
set_property IOSTANDARD LVDS_25 [get_ports cmos1_clk_hs_rxp]
set_property IOSTANDARD LVDS_25 [get_ports cmos1_clk_hs_rxn]
# low power
set_property IOSTANDARD LVCMOS18 [get_ports cmos1_clk_lp_rxp]
set_property IOSTANDARD LVCMOS18 [get_ports cmos1_clk_lp_rxn]
set_property IOSTANDARD LVDS_25 [get_ports cmos1_data_hs_rxp]
set_property IOSTANDARD LVDS_25 [get_ports cmos1_data_hs_rxn]
set_property IOSTANDARD LVCMOS18 [get_ports cmos1_data_lp_rxp]
set_property IOSTANDARD LVCMOS18 [get_ports cmos1_data_lp_rxn]
set_property PACKAGE_PIN K18 [get_ports cmos1_clk_hs_rxn]
set_property PACKAGE_PIN K17 [get_ports cmos1_clk_hs_rxp]
set_property PACKAGE_PIN M19 [get_ports cmos1_clk_lp_rxp]
set_property PACKAGE_PIN M20 [get_ports cmos1_clk_lp_rxn]
set_property PACKAGE_PIN J19 [get_ports cmos1_data_hs_rxn]
set_property PACKAGE_PIN K19 [get_ports cmos1_data_hs_rxp]
set_property PACKAGE_PIN J20 [get_ports cmos1_data_lp_rxp]
set_property PACKAGE_PIN H20 [get_ports cmos1_data_lp_rxn]

## dphy cmos2
set_property IOSTANDARD LVDS_25 [get_ports cmos2_clk_hs_rxp]
set_property IOSTANDARD LVDS_25 [get_ports cmos2_clk_hs_rxn]
# low power
set_property IOSTANDARD LVCMOS18 [get_ports cmos2_clk_lp_rxp]
set_property IOSTANDARD LVCMOS18 [get_ports cmos2_clk_lp_rxn]
set_property IOSTANDARD LVDS_25 [get_ports cmos2_data_hs_rxp]
set_property IOSTANDARD LVDS_25 [get_ports cmos2_data_hs_rxn]
set_property IOSTANDARD LVCMOS18 [get_ports cmos2_data_lp_rxp]
set_property IOSTANDARD LVCMOS18 [get_ports cmos2_data_lp_rxn]
set_property PACKAGE_PIN H17 [get_ports cmos2_clk_hs_rxn]
set_property PACKAGE_PIN H16 [get_ports cmos2_clk_hs_rxp]
#set_property PACKAGE_PIN H15 [get_ports cmos2_clk_lp_rxp]
#set_property PACKAGE_PIN G15 [get_ports cmos2_clk_lp_rxn]
set_property PACKAGE_PIN G15 [get_ports cmos2_clk_lp_rxp]
set_property PACKAGE_PIN H15 [get_ports cmos2_clk_lp_rxn]
set_property PACKAGE_PIN L17 [get_ports cmos2_data_hs_rxn]
set_property PACKAGE_PIN L16 [get_ports cmos2_data_hs_rxp]
set_property PACKAGE_PIN M17 [get_ports cmos2_data_lp_rxp]
set_property PACKAGE_PIN M18 [get_ports cmos2_data_lp_rxn]

set_property DIFF_TERM FALSE [get_ports cmos1_clk_hs_rxp]
set_property DIFF_TERM FALSE [get_ports cmos1_clk_hs_rxn]
set_property DIFF_TERM FALSE [get_ports cmos1_data_hs_rxp]
set_property DIFF_TERM FALSE [get_ports cmos1_data_hs_rxn]
##
set_property DIFF_TERM FALSE [get_ports cmos2_clk_hs_rxp]
set_property DIFF_TERM FALSE [get_ports cmos2_clk_hs_rxn]
set_property DIFF_TERM FALSE [get_ports cmos2_data_hs_rxp]
set_property DIFF_TERM FALSE [get_ports cmos2_data_hs_rxn]

 

 

There are others pins like sensor I2C, which is lvcmos 1.8...

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florentw
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Hi @young1988,

 

Thanks. I will have a look

 

Just to check: you do not have this error if calibration mode is set to none, right?

 

Regards,

 

Florent


Florent
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young1988
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yes! When anyone of the two core works in none calibration mode, the error dispears. It olny happens when both cores works in calibration mode!

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young1988
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Hi, @florentw,

 

Is there some  news about this issue?

 

Regards,

 

Bruce He

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florentw
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Hi @young1988,

 

I didn't have time yesterday. I will try to reproduce what you see today.

 

Regards,

 

Florent


Florent
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florentw
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Hi @young1988,

 

I can reproduce the error message you get. I am investigating.

 

Regards,

 

Florent


Florent
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young1988
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Hi Florent,

 

I am looking forward for any news about this issue, THX!

 

 Chao He

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florentw
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Hi @young1988 Chao He,

 

Sorry this got lost during the Xmas holiday. Let me get back to you before the end of week.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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Hi @young1988,

 

Could you try with 2017.4? The issue should have been fixed.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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