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Adventurer
Adventurer
528 Views
Registered: ‎10-20-2019

Errors in mipi csi-2 rx

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I used mipi csi-2 ip to receive the mipi signal,there are some errors.

My design is shown below.

2020-09-08_093547.png

Image1 is shown below.

2020-09-07_113502.png

Image2 is shown below.

2020-09-07_113222.png

Other information:

zfzs.png

2020-09-08_100346.png

https://forums.xilinx.com/t5/Video-and-Audio/mipi-csi2-ip-design-with-Ti-DS90UB953A-Q1-and-DS90UB954-Q1/m-p/1147619#M34246

 

So, I think there are some problems in  FPGA  mipi RX.

The ila and register dump of mipi csi-2 rx is attached.

@karnanl 

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Xilinx Employee
Xilinx Employee
256 Views
Registered: ‎03-30-2016

Hello @xxwang 

Since you already enabled "D-PHY register interface", you can set IDELAY_TAP via register.
Please see also IDELAY_TAP setting register (see also PG202 Chapter 3).

You can use xsct to write/read the IDELAY_TAP register. Something like this:
(a) So, write MIPI D-PHY register (address 0x4) with a new IDELAY_TAP_VALUE value .
(b) Read back the register to ensure you set the correct value.
(c) Clear MIPI CSI-2 RX Subsystem ISR register (address : 0x24), after you changed MIPI D-PHY RX IDELAY_TAP_VALUE.
(d) Re-read MIPI CSI-2 RX Subsystem ISR register, please notice if you have some improvement on the error flag shown in register 0x24.
(e) Repeat step (a)

Regards
Leo

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Adventurer
Adventurer
468 Views
Registered: ‎10-20-2019

Hello,  

Could you help explain the Calibration Mode of mipi csi-2 rx ip to me ?

And how to calculate  the correct IDELAY Tap Value?

Best Regards!

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Xilinx Employee
Xilinx Employee
456 Views
Registered: ‎03-30-2016

Hello Wang @xxwang 

Thanks for sharing your data, I just confirmed your register dump.

xsct% mrd 0x44A20024
44A20024: 800A2E03
  [0]Frame level error for VC0
  [1]Frame synchronization error for VC0
  [9]CRC error
  [10]ECC 1-bit error
  [11]ECC 2-bit error
  [13]SoT error (ErrSoTHS)


I can see that the following error flags are asserted, so we need to fix this.
  [9]CRC error
  [10]ECC 1-bit error
  [11]ECC 2-bit error
  [13]SoT error (ErrSoTHS)

I am aware you don't have an oscilloscope on your lab right now, but since CRC error occurs I am assuming that your system does not follow Data to Clock Timing spec as mentioned below.
MIPI_D-PHY_CLOCK_LANE_SETUP_HOLD.png

So maybe you need to some experiment using IDELAY_TAP setting register (see also PG202 Chapter 3)

IDELAY_TAP_VAL.png

Your current MIPI CSI-2 RX IP configuration is as follow:
WANG_RX_configuration.png

You need to (1)~(3) to change IDELAY_TAP_VALUE of each line on-the-fly
    (1) Set Calibration Mode as "FIXED"
    (2) Enable "D-PHY Register Interface"
    (3) And regenerate your design.

At this point you are ready to do IDELAY_TAP value manual calibration.
(a) So, please re-test your design, the IDELAY_TAP_VALUE default value for data-lane[0] and [1] should be "1" (or any value you set on the GUI).
(b) You need to increase the IDELAY_TAP_VALUE for both lane[0]&[1], little by little
     For example : 1,3,5,7, .....
(c) Please clear MIPI CSI-2 RX Subsystem ISR register ( address : 0x24) , after you changed MIPI D-PHY RX IDELAY_TAP_VALUE.
(d) Re-read MIPI CSI-2 RX Subsystem ISR register, please notice if you have some improvement on the error flag shown in register 0x24.
(e) Repeat step (b)

Our first goal in this manual calibration is to find suitable IDELAY_TAP_VALUE on your system ,
So no can no longer see the following error flags asserted.
  [9]CRC error
  [10]ECC 1-bit error
  [11]ECC 2-bit error
  [13]SoT error (ErrSoTHS)


Please let me know, if this is not clear for you.

Kind regards
Leo

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

Is  the Data to Clock Timing spec defined in mipi D-PHY spec?

But the test below used the same hardware, it worked. no error occured in mipi rx ip register dump.

zfzs.png

I have configured MIPI CSI-2 RX IP as below, not including  step (2) Enable "D-PHY Register Interface". Is step (2) necessary?

2020-09-08_171227.png

I have tested  the IDELAY Tap Value in GUI  as 1,2,3,4. The ISR register value is all the same as below.

2020-09-08_172335.png

  [0]Frame level error for VC0
  [9]CRC error
  [10]ECC 1-bit error

Best Regards!

 

 

 

 

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Xilinx Employee
Xilinx Employee
441 Views
Registered: ‎03-30-2016

Hello @xxwang 

>Is the Data to Clock Timing spec defined in mipi D-PHY spec?

Yes, please see the MIPI D-PHY spec. chapter 10.
Especially "10.2 Forward High-Speed Data Transmission Timing" section.

>But the test below used the same hardware, it worked. no error occured in mipi rx ip register dump.

The signals connectivity are not exactly the same between those systems.
Okay, I don't have the waveform shot from your board to prove this assumption.
But, since you got CRC errors on your board, I am assuming there are some pattern lenght deviation between clock and data lanes in your HW,
If this is the case we can adjust with IDELAY_TAP_VALUE.

>I have configured MIPI CSI-2 RX IP as below, not including step (2) Enable "D-PHY Register Interface". Is step (2) necessary?

It is your choice.

(a) You can generate each bitfile with different IDELAY_TAP_VALUE , and test each setting on your board.
Using this method, you will need to generate bitfiles for each IDELAY_TAP_VALUE configuration.

If you have many PC/workstation to run multiple design implementation, I do not see any issue with this method.
But please sweep all the configurable IDELAY_TAP_VALUE from 1 to 31.
( You need to increment IDELAY_TAP_VALUE by 2 or 3, so you don't need to generate all 31 bitfiles )

(b) Or as an alternative you can also , Enable "D-PHY Register Interface".
And do this IDELAY_TAP_VALUE modification , by changing MIPI D-PHY register setting.
You need to clear ISR register , after modified IDELAY_TAP_VALUE register.

> [0]Frame level error for VC0
> [9]CRC error
> [10]ECC 1-bit error

I think you went to the right direction, since we can see that errors are decreased.
Would you able to test IDELAY_TAP_VALUE=7,10,13,16,.... ?

Regards
Leo

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

Thank you for your reply.

I have tested all the configurable IDELAY_TAP_VALUE from 1 to 31,ISR register is the same as '0x80020601'.

How to modify  IDELAY_TAP_VALUE  by changing MIPI D-PHY register setting ?

I read the register from command line tool, but it seems not correct.

Could the 'Tap value for lane0' and the 'Tap value for lane1' be different value?

2020-09-10_115452.png

2020-09-10_115704.png

2020-09-10_115603.png

Best Regards!

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

The test results are different whether I  enable "D-PHY Register Interface". Why?

I think the method I configured IDELAY_TAP_VALUE maybe not correct.

Best Regards!

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Xilinx Employee
Xilinx Employee
374 Views
Registered: ‎03-30-2016

Hello @xxwang 

Thank you for updating your status.

1. Are you using video_aclk=100MHz or higher frequency clock ?
   ( I need check this clock freq, since your MIPI usecase is different from the last thread )

2. I have tested all the configurable IDELAY_TAP_VALUE from 1 to 31,ISR register is the same as '0x80020601'.

Thank you for the test. I believe your test result is using
    (a) D-PHY Register Interface : Disable
    (b) With IDELAY TAP Value configured from the GUI.

3. The test results are different whether I enable "D-PHY Register Interface". Why?
    I think the method I configured IDELAY_TAP_VALUE maybe not correct.

Hmm, interesting result.
I will check and give you a feedback on this. Please wait.
Let me generate some MIPI CSI-2 RX IP and see something different with "D-PHY Register Interface" enable/disable.

4. How to modify IDELAY_TAP_VALUE by changing MIPI D-PHY register setting ?

IDELAY_TAP setting register (see also PG202 Chapter 3)
IDELAY_TAP_VAL.png
You can access this register if you enabled "D-PHY Register Interface".
Please note that you need to clear ISR register after you set a new IDELAY_TAP value.

5. Could the 'Tap value for lane0' and the 'Tap value for lane1' be different value?

Yes.

Thanks & regards
Leo

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Adventurer
Adventurer
364 Views
Registered: ‎10-20-2019

Hello, @karnanl 

1. Yes, it is 100MHz.

2.Yes.

3.OK. The test result is using
    (a) D-PHY Register Interface : Disable/Enable
    (b) With IDELAY TAP Value configured from the GUI.

4.Could the register be read or writed in command line tool?

I read the register from command line tool after I enable the D-PHY Register Interface, but it seems not correct.

2020-09-10_115452.png

Best Regards!

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @xxwang 

video_aclk=100MHz should be fine. Thanks.

>Could the register be read or writed in command line tool?

IDELAY_TAP_VALUE register should be accessible from reg address (0x4).

>I read the register from command line tool after I enable the D-PHY Register Interface, but it seems not correct.

Do you mean (a) or (b) , could you please clarify ?
   (a) the IDELAY_TAP_VALUE you have set on the GUI, cannot be confirmed when you read reg 0x4
   (b) You write a new IDELAY_TAP_VALUE on reg 0x4, but when you read back the register, the value has not changed.

Regards
Leo

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

Do you mean (a) or (b) , could you please clarify ?
   (a) the IDELAY_TAP_VALUE you have set on the GUI, cannot be confirmed when you read reg 0x4
   (b) You write a new IDELAY_TAP_VALUE on reg 0x4, but when you read back the register, the value has not changed.

I mean (a).

If there are Data to Clock Timing problems in my system, could these problems be solved by using  IDELAY_TAP_VALUE ?

Best Regards!

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @xxwang 

BTW, did you enable "Include IDELAYCTRL in core" option when you generate your MIPI CSI-2 RX IP ?

IDELAY_CTRL.png

>If there are Data to Clock Timing problems in my system, could these problems be solved by using IDELAY_TAP_VALUE ?


IDELAY_TAP_VALUE can help to adjust Clock and Data lane skew, so ISERDES module can capture the data correctly.
# This is will not solve a timing related issue in your design, if there are a timing violations in your design you need to fix them.

Thanks & regards
Leo

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Adventurer
Adventurer
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Registered: ‎10-20-2019

Hello, @karnanl 

BTW, did you enable "Include IDELAYCTRL in core" option when you generate your MIPI CSI-2 RX IP ?

YES.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @xxwang 

Okay, so IDELAYCTRL is also implemented in your design.


wang_analysis_GUI_setting.png

For 7-series devices, I found that MIPI CSI-2 RX Subsystem may not configured correctly with
- Fixed Calibration mode
- D-PHY register interface : Disable
Please notice that IDELAY_TYPE should be configured FIXED , rather than VAR_LOAD.
I will give our IP development team feedback on this. Please wait.

For now, could you please use "D-PHY register interface : Enable" setting, when using Fixed Calibration mode ??


Regards
Leo

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Adventurer
Adventurer
261 Views
Registered: ‎10-20-2019

Hello, @karnanl 

Thank you for your reply.

I need to confirm some information with you.

When I use "D-PHY register interface : Enable"  &  “Fixed Calibration mode”  How to set the IDELAY_TAP_VALUE ?

I should set the IDELAY_TAP_VALUE in GUI or in command line tool or in Vitis code?

Could you please provide me a detailed instruction or a demo vitis project ? 

Thank you!

Best Regards!

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Xilinx Employee
Xilinx Employee
257 Views
Registered: ‎03-30-2016

Hello @xxwang 

Since you already enabled "D-PHY register interface", you can set IDELAY_TAP via register.
Please see also IDELAY_TAP setting register (see also PG202 Chapter 3).

You can use xsct to write/read the IDELAY_TAP register. Something like this:
(a) So, write MIPI D-PHY register (address 0x4) with a new IDELAY_TAP_VALUE value .
(b) Read back the register to ensure you set the correct value.
(c) Clear MIPI CSI-2 RX Subsystem ISR register (address : 0x24), after you changed MIPI D-PHY RX IDELAY_TAP_VALUE.
(d) Re-read MIPI CSI-2 RX Subsystem ISR register, please notice if you have some improvement on the error flag shown in register 0x24.
(e) Repeat step (a)

Regards
Leo

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