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Observer
Observer
3,919 Views
Registered: ‎02-11-2011

Evaluation of Synthesis Report

Hello,

 

i implemented the JPEG-LS algorithm for my master thesis with system generator. Now i synthesized my model i i become the report in the attachment.

Can anybody say me, what is important in this algorithm, and if the results are good or not? I'm a really beginner in the fpga section, and i don't know how to evaluate this report. I only think 16,xxx Mhz is very slow for such a simple algorithm or not?

 

Thx in advance,

Sibianu

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Xilinx Employee
Xilinx Employee
3,817 Views
Registered: ‎08-01-2007

The problem is that you don't have any pipelining.  This works okay in software, and maybe in an ASIC, but FPGAs are register rich so you get your best performance when you add pipelining to your design.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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Highlighted
3,811 Views
Registered: ‎01-09-2010

Levels of Logic is too large. Add enough Register to reduce it.
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