12-06-2019 10:32 AM - last edited on 12-09-2019 12:22 AM by florentw
I want to generate the video signals which I can use to feed as an input to the DisplayPort TX subsystem(Native stream). Our team has created design which are using video test pattern generator,video timing controller and AXI4 stream to video out IP's to generate the test pattern.
I want to individually test this design using ILA before connecting it to DP TX subsystem. But I have below concerns:
1) Is there any Video Test pattern generator example code to generate the video of specified timings ?
2) Is it mandatory to use CLK_WIZ IP ?
12-09-2019 06:52 PM
>2) Is it mandatory to use CLK_WIZ IP ?
But you must change pll setting via DRP interface.
Refer page 4 of the following URL.
12-10-2019 01:43 AM - edited 12-10-2019 01:43 AM
The video test pattern generator is an helper core available only in the Displayport example designs. It is not supported outside the example designs.
The only example are the Displayport example designs.
You might want to consider the Xilinx Test Pattern Generator which is part of the IP catalog. However, please note that the user is expected to map the video streams on the lanes for the displayport Tx. This mapping will change depending on how many lanes are trained