10-02-2019 11:18 AM
Hello, I am doing a design for a PCB board that will need to interface with 4-SDI cameras. I am looking a the SMPTE UHD-SDI Receiver Subsystem v2.0 document and in particular the required external clocks for the IP. I am expecting to following Figure 1-1 in the IP datasheet:
I am currently doing the PCB design and trying to allocate the appropriate number of clocks I will need.
Am I correct that the "sdi_rx_clk" input to the IP is a required external clock input?
Also, the "video_out_clk" input that must be the clock from the SDI camera am correct? This is my first experience with SDI cameras.
10-02-2019 07:06 PM
Since you are using SMPTE UHD-SDI receiver subsystem, we would like to suggest the same.
Please generate example design and check yourself.
sdi_rx_clk is coming from transceiver (PHY)
>"video_out_clk" input that must be the clock from the SDI camera am correct?
No, not necessary.
Thanks & regards
10-03-2019 06:51 AM
Hello, thank you for responding to my message. Quick question for, does the IP only support a single SDI stream? I need to interface with 4-SDI cameras. I'm desiging a board that will receive 4-SDI Video streams, and then send each stream over fiber, now on the receiving board I will convert the data back to SDI and then send it to SDI capable monitors or to a frame grabber. It would be nice if I could find an IP that could support 4-RX only streams and 4-TX only streams so in each case I would only need 2 external reference clocks, one for the TX and one for the RX.
If you have any comments please share them with me please.