FIR Implementation

[assaf_malki]

Hey guys,

I'm using Virtex 5 70T.

In my design I need to use 3 FIRs. For each of them I'm using coefficients width of 32 bits because it gives me the best result.

The problem is it uses to many of the DSP48E slices.

I tried using less bits for the coefficients but the results I'm getting is not good to say the less.

In the attachments you can see the settings I use for the FIR.

Any suggestions?

Thanks a lot.

Assaf.

[bwiec]

What's your clock rate and sample rate? Setting the hardware oversampling period to 1 will give you a full parallel implementation (assuming your simulink system period is also set to 1). If you can oversample (i.e. use a faster clock than sample rate), resources will be shared and potentially save you a lot of DSP slices, depending on how much oversampling you can do.