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Newbie
Newbie
707 Views
Registered: ‎05-09-2019

FPGA product information inquiry: 29 x 2-lane MIPI CSI-2 @ 1.5 Gbps (with on chip D-PHY)

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Hi,

We are looking for an FPGA which can accept images from 29 MIPI CSI-2 interfaces each with 2 lanes; the speed per lane must be 1.5 Gbps.

Also, we don't have space to make use of external components such as http://meticom.com/page2/Products.html or similar or a passive resistor network.

From the FPGA we want to interface 64bit DDR4 and an ethernet phy as well.

Does Xilinx have an FPGA device+package which meets these requirements (especially regarding MIPI CSI-2)?

In any case that would be fantastic!

Many thanks in advance for your answer.

Kind regards,

Ilse de Moffarts

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Xilinx Employee
Xilinx Employee
644 Views
Registered: ‎03-30-2016

Hello Ilse de Moffarts @ilse_dm 

1. You need to use UltraScale+ devices. (Zynq MPSoC or Kintex UltraScale+)
2. Each US+ HP I/O bank can accomodate up to 2-lanes x 8-instances of MIPI. (Please see PG202 Chapter 4)
3. So, 4 HP I/O banks are needed to accomodate your 29 MIPI instances.
4. 2 HP I/O banks are needed to accomodate you DDR4 I/F.
5. You can use GTH to accomodate your Ethernet I/F.

6. Device that may fit your system requirement is :
    ( Please check UG1075 Table 1-3, Table 1-6)
    -- Perhaps any Zynq MPSoC with package bigger than 1517 should fit your system requirement.
    -- Some device with (ffvc1156) package may do the job too.


-- Suggest you to contact Distributor/Xilinx FAE for this kind of questions.
    They can give you perfect solution on device selection to meet your system requirement.
-- As mentioned in PG202, MIPI IP I/F has some constraint on pin-assignments.
    Please read appendix C also, and it would be great if you can a sample FPGA design to test pin-assignment before designing your board.

Hope this helps.

 

Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
645 Views
Registered: ‎03-30-2016

Hello Ilse de Moffarts @ilse_dm 

1. You need to use UltraScale+ devices. (Zynq MPSoC or Kintex UltraScale+)
2. Each US+ HP I/O bank can accomodate up to 2-lanes x 8-instances of MIPI. (Please see PG202 Chapter 4)
3. So, 4 HP I/O banks are needed to accomodate your 29 MIPI instances.
4. 2 HP I/O banks are needed to accomodate you DDR4 I/F.
5. You can use GTH to accomodate your Ethernet I/F.

6. Device that may fit your system requirement is :
    ( Please check UG1075 Table 1-3, Table 1-6)
    -- Perhaps any Zynq MPSoC with package bigger than 1517 should fit your system requirement.
    -- Some device with (ffvc1156) package may do the job too.


-- Suggest you to contact Distributor/Xilinx FAE for this kind of questions.
    They can give you perfect solution on device selection to meet your system requirement.
-- As mentioned in PG202, MIPI IP I/F has some constraint on pin-assignments.
    Please read appendix C also, and it would be great if you can a sample FPGA design to test pin-assignment before designing your board.

Hope this helps.

 

Thanks & regards
Leo

View solution in original post

Newbie
Newbie
611 Views
Registered: ‎05-09-2019

Great! Thank you very much for your answer.

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